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公开(公告)号：US20140095927A1
公开(公告)日：2014-04-03
申请号：US13925696
申请日：2013-06-24
发明人： Vineet M. Abraham , Bill Ying Chin , William R. Mahoney , Aditya Saxena , Xupei Liang , Bill Jianqiang Zhou
IPC分类号： G06F11/20
CPC分类号： G06F11/2017 , G06F11/00 , G06F11/1482 , G06F11/20
摘要： Techniques for achieving high-availability using a single processor (CPU). In a system comprising a multi-core processor, at least two partitions may be configured with each partition being allocated one or more cores of the multiple cores. The partitions may be configured such that one partition operates in active mode while another partition operates in standby mode. In this manner, a single processor is able to provide active-standby functionality, thereby enhancing the availability of the system comprising the processor.
摘要翻译： 使用单处理器（CPU）实现高可用性的技术。 在包括多核处理器的系统中，可以配置至少两个分区，其中每个分区被分配多个核的一个或多个核。 分区可以被配置为使得一个分区在活动模式下操作，而另一个分区在待机模式下操作。 以这种方式，单个处理器能够提供主动 - 待机功能，从而增强包括处理器的系统的可用性。
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公开(公告)号：US09026848B2
公开(公告)日：2015-05-05
申请号：US13925696
申请日：2013-06-24
发明人： Vineet M. Abraham , Bill Ying Chin , William R. Mahoney , Aditya Saxena , Xupei Liang , Bill Jianqiang Zhou
CPC分类号： G06F11/2017 , G06F11/00 , G06F11/1482 , G06F11/20
摘要： Techniques for achieving high-availability using a single processor (CPU). In a system comprising a multi-core processor, at least two partitions may be configured with each partition being allocated one or more cores of the multiple cores. The partitions may be configured such that one partition operates in active mode while another partition operates in standby mode. In this manner, a single processor is able to provide active-standby functionality, thereby enhancing the availability of the system comprising the processor.
摘要翻译： 使用单处理器（CPU）实现高可用性的技术。 在包括多核处理器的系统中，可以配置至少两个分区，其中每个分区被分配多个核的一个或多个核。 分区可以被配置为使得一个分区在活动模式下操作，而另一个分区在待机模式下操作。 以这种方式，单个处理器能够提供主动 - 待机功能，从而增强包括处理器的系统的可用性。
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公开(公告)号：US20160182241A1
公开(公告)日：2016-06-23
申请号：US14923327
申请日：2015-10-26
IPC分类号： H04L12/18 , H04L12/721
CPC分类号： H04L12/18 , H04L12/185 , H04L45/16 , H04L45/60 , H04L45/66 , H04L47/15 , H04L49/201 , H04L51/28
摘要： Certain embodiments of the present invention provide techniques that enable messages to be sent to a processing entity within a computing device without knowing the network address of the processing entity. In certain embodiments, instead of using the network address of the processing entity, a message can be communicated to the processing entity using information indicative of a role or state or function performed by the processing entity.
摘要翻译： 本发明的某些实施例提供了使消息能够在不知道处理实体的网络地址的情况下发送到计算设备内的处理实体的技术。 在某些实施例中，代替使用处理实体的网络地址，可以使用指示由处理实体执行的角色或状态或功能的信息将消息传送到处理实体。
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公开(公告)号：US09203690B2
公开(公告)日：2015-12-01
申请号：US13827641
申请日：2013-03-14
IPC分类号： G06F15/173 , H04L12/24 , H04L12/58 , H04L12/801 , H04L12/761 , H04L12/773
摘要： Certain embodiments of the present invention provide techniques that enable messages to be sent to a processing entity within a computing device without knowing the network address of the processing entity. In certain embodiments, instead of using the network address of the processing entity, a message can be communicated to the processing entity using information indicative of a role or state or function performed by the processing entity.
摘要翻译： 本发明的某些实施例提供了使消息能够在不知道处理实体的网络地址的情况下发送到计算设备内的处理实体的技术。 在某些实施例中，代替使用处理实体的网络地址，可以使用指示由处理实体执行的角色或状态或功能的信息将消息传送到处理实体。
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5.发明申请公开(公告)号：US20150081986A1
公开(公告)日：2015-03-19
申请号：US14329767
申请日：2014-07-11
CPC分类号： G06F9/467 , G06F3/0617 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F9/544 , G06F11/141 , G06F11/1471 , G06F11/1474 , G06F12/0284 , G06F15/167 , G06F2201/84 , G06F2201/87 , G06F2212/1041
摘要： Techniques are provided for reliable and efficient access to non-transactional resources using transactional memory. In certain aspects, a device may include memory and one or more processing entities, configurable to execute a first transaction comprising one or more write operations to a first memory address, and a second transaction comprising one or more write operations to a second memory address. The first memory address and the second memory address may be mapped to the same controller for a hardware component and the one or more processing entities may commence execution of the second transaction after the first transaction starts execution and before the completion of the first transaction. The device may also include a transactional memory system configurable to communicate data written to the first memory address from the first transaction and the second memory address from the second transaction to the controller upon completion of the respective transactions.
摘要翻译： 提供了使用事务性内存来可靠和高效地访问非事务性资源的技术。 在某些方面，设备可以包括存储器和一个或多个处理实体，可配置为执行包括对第一存储器地址的一个或多个写操作的第一事务，以及包括对第二存储器地址的一个或多个写操作的第二事务。 第一存储器地址和第二存储器地址可以被映射到硬件组件的相同控制器，并且一个或多个处理实体可以在第一事务开始执行之后和第一事务完成之前开始第二事务的执行。 该设备还可以包括事务存储器系统，可配置为在完成相应的事务时将从第一事务写入第一存储器地址的数据和第二存储器地址从第二事务传送到控制器。
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公开(公告)号：US20150074219A1
公开(公告)日：2015-03-12
申请号：US14266517
申请日：2014-04-30
IPC分类号： G06F15/167 , H04L29/08
CPC分类号： G06F9/467 , G06F3/0617 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F9/544 , G06F11/141 , G06F11/1471 , G06F11/1474 , G06F12/0284 , G06F15/167 , G06F2201/84 , G06F2201/87 , G06F2212/1041
摘要： Techniques for facilitating high availability in a device (e.g., a network device) comprising redundant processing entities (e.g., one or more processors, one or more cores, etc.) and a transactional memory system. The transactional memory system comprises a memory that is shareable between the redundant processing entities and ensures consistency of information stored in the memory at the atomicity of a transaction. A first processing entity may operate in a first mode (e.g., active mode) while a second processing entity operates in a second mode (e.g., standby mode). Operational state information used by the active processing entity for performing a set of functions in the first mode may be stored in the shared memory. Upon a switchover, the second processing entity may start to operate in the first mode and commence performing the set of functions using the operational state information stored by the transactional memory system.
摘要翻译： 用于促进包括冗余处理实体（例如，一个或多个处理器，一个或多个核心等）和事务存储器系统的设备（例如，网络设备）中的高可用性的技术。 事务存储器系统包括可在冗余处理实体之间共享的存储器，并确保以事务的原子性存储在存储器中的信息的一致性。 第一处理实体可以以第一模式（例如，活动模式）操作，而第二处理实体在第二模式（例如，待机模式）中操作。 活动处理实体用于执行第一模式中的一组功能的操作状态信息可以被存储在共享存储器中。 在切换时，第二处理实体可以开始以第一模式操作，并且使用事务存储器系统存储的操作状态信息开始执行功能集。
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公开(公告)号：US20140007097A1
公开(公告)日：2014-01-02
申请号：US13796136
申请日：2013-03-12
发明人： Bill Ying Chin , Vineet M. Abraham
IPC分类号： G06F9/455
CPC分类号： G06F9/455 , G06F9/45533 , G06F9/5016 , G06F9/5077
摘要： Certain embodiments enable resources assigned or allocated to an operating virtual machine (VM) to be modified while the VM is operating and without having to stop, restart, or reboot the VM. The modification may correspond to increasing or decreasing the amount of a resource being assigned to the VM. In this manner, resources assigned to a VM at the time of creation of the VM are not static and can instead be dynamically changed while the VM is operating without having to stop, reboot, or restart the VM. In some embodiments, the changes to the resources allocated to one or more VMs provided for a user (e.g., a customer) may be made according to or in response to a Service Level Agreement (SLA) entered into by the user, in response to an event such as a failover or switchover event, and the like.
摘要翻译： 某些实施例使得在VM正在操作而不必停止，重新启动或重新引导VM的情况下修改分配给或分配给操作虚拟机（VM）的资源。 修改可以对应于分配给VM的资源的数量的增加或减少。 以这种方式，在创建VM时分配给VM的资源不是静态的，而是可以在VM运行时动态地更改，而不必停止，重新启动或重新启动VM。 在一些实施例中，可以根据或响应于用户输入的服务水平协议（SLA）来为分配给用户（例如，客户）的一个或多个VM分配的资源的改变，以响应于 诸如故障切换或切换事件的事件等。
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公开(公告)号：US20170199760A1
公开(公告)日：2017-07-13
申请号：US15471991
申请日：2017-03-28
CPC分类号： G06F9/467 , G06F3/0617 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F9/544 , G06F11/141 , G06F11/1471 , G06F11/1474 , G06F12/0284 , G06F15/167 , G06F2201/84 , G06F2201/87 , G06F2212/1041
摘要： Techniques are disclosed for generating a multi-transactional system using transactional memory techniques. According to certain embodiments, a device may include a memory, one or more processing entities, and a transactional memory system for maintaining a plurality of transactional memory (TM) logs in a first portion of the memory. Each TM log may be associated with one transaction from a plurality of transactions sequentially executed by the one or more processing entities and each transaction comprises a plurality of operations. Furthermore, each TM log associated with each transaction comprises information associated with changes to a second portion of the memory caused by execution of operations from the transaction using the one or more processing entities. The TM logs for completed transactions may be used for error detection and recovery and maintaining high availability of the device.
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公开(公告)号：US20150082085A1
公开(公告)日：2015-03-19
申请号：US14329720
申请日：2014-07-11
CPC分类号： G06F9/467 , G06F3/0617 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F9/544 , G06F11/141 , G06F11/1471 , G06F11/1474 , G06F12/0284 , G06F15/167 , G06F2201/84 , G06F2201/87 , G06F2212/1041
摘要： Techniques are disclosed for generating a multi-transactional system using transactional memory techniques. According to certain embodiments, a device may include a memory, one or more processing entities, and a transactional memory system for maintaining a plurality of transactional memory (TM) logs in a first portion of the memory. Each TM log may be associated with one transaction from a plurality of transactions sequentially executed by the one or more processing entities and each transaction comprises a plurality of operations. Furthermore, each TM log associated with each transaction comprises information associated with changes to a second portion of the memory caused by execution of operations from the transaction using the one or more processing entities. The TM logs for completed transactions may be used for error detection and recovery and maintaining high availability of the device.
摘要翻译： 公开了用于使用事务性存储器技术生成多事务系统的技术。 根据某些实施例，设备可以包括存储器，一个或多个处理实体和用于在存储器的第一部分中维护多个事务存储器（TM）日志的事务存储器系统。 每个TM日志可以与由一个或多个处理实体顺序执行的多个事务中的一个事务相关联，并且每个事务包括多个操作。 此外，与每个事务相关联的每个TM日志包括与由使用一个或多个处理实体的事务执行操作引起的对存储器的第二部分的改变相关联的信息。 用于完成事务的TM日志可用于错误检测和恢复，并保持设备的高可用性。
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公开(公告)号：US20140089484A1
公开(公告)日：2014-03-27
申请号：US13827641
申请日：2013-03-14
IPC分类号： H04L12/24
摘要： Certain embodiments of the present invention provide techniques that enable messages to be sent to a processing entity within a computing device without knowing the network address of the processing entity. In certain embodiments, instead of using the network address of the processing entity, a message can be communicated to the processing entity using information indicative of a role or state or function performed by the processing entity.
摘要翻译： 本发明的某些实施例提供了使消息能够在不知道处理实体的网络地址的情况下发送到计算设备内的处理实体的技术。 在某些实施例中，代替使用处理实体的网络地址，可以使用指示由处理实体执行的角色或状态或功能的信息将消息传送到处理实体。
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