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公开(公告)号:US11538385B2
公开(公告)日:2022-12-27
申请号:US17355858
申请日:2021-06-23
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Zhichong Wang , Guangcai Yuan , Fuqiang Li , Jing Feng , Xinglong Luan , Peng Liu
IPC: G09G3/20 , G09G3/36 , G09G3/3266 , G06F3/041
Abstract: A gate driving unit includes: a pull-up node denoising circuit; a pull-down node control circuit; a pull-up node control circuit; and an energy storage circuit. The pull-up node denoising circuit is configured to, under control of a potential of the pull-down node, control coupling or discoupling between the first pull-up node and the input terminal. The pull-down node control circuit is configured to, under control of a control voltage, control the potential of the pull-down node; under control of a potential of the second pull-up node, control coupling or discoupling between the pull-down node and the input terminal. The pull-up node control circuit is configured to, under control of an anti-leakage control voltage, control coupling or discoupling between the first pull-up node and the second pull-up node, and configured to maintain the potential of the second pull-up node. The energy storage circuit is configured to store electric energy.
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公开(公告)号:US11409202B2
公开(公告)日:2022-08-09
申请号:US17199395
申请日:2021-03-11
Applicant: BOE Technology Group Co., Ltd.
Inventor: Xinglong Luan , Fuqiang Li , Jing Feng , Zhichong Wang , Peng Liu , Guangcai Yuan , Xue Dong
Abstract: Provided is a digital exposure control method, including: performing exposure of different types of functional areas of a substrate to be exposed through one or a plurality of full-page scans, wherein scan speeds for different types of functional areas of the substrate to be exposed are different.
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公开(公告)号:US11227525B2
公开(公告)日:2022-01-18
申请号:US16769910
申请日:2020-01-08
Inventor: Zhichong Wang , Fuqiang Li , Peng Liu , Jing Feng , Xinglong Luan
Abstract: A shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes: an input sub-circuit configured to transmit a signal at an input signal terminal to a first node under control of a voltage at a second node; a discharging control sub-circuit configured to transmit a signal at a first clock signal terminal to the second node under control of a voltage at the first node; a discharging sub-circuit configured to transmit a signal at a first constant voltage signal terminal to an output signal terminal under control of the voltage at the second node; and an output sub-circuit configured to transmit a signal at a second clock signal terminal to the output signal terminal under control of the voltage at the first node.
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公开(公告)号:US11189679B2
公开(公告)日:2021-11-30
申请号:US16711972
申请日:2019-12-12
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Jing Feng , Dongsheng Yin , Ce Ning , Jiushi Wang
Abstract: An array substrate includes a base substrate and a plurality of pixel units disposed on a base substrate, and at least one pixel unit includes a plurality of thin film transistors, a first electrode, and a second electrode. The plurality of thin film transistors include at least one first thin film transistor including a first active pattern, a first gate, a first source and a first drain. The first electrode is disposed in a same layer as the first active pattern, the first electrode is coupled to the first drain, and the second electrode is disposed in a same layer as the first gate. Orthographic projections of any two in a group consisting of the first electrode, the second electrode, and the first drain on the base substrate have an overlapping region.
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公开(公告)号:US09784904B2
公开(公告)日:2017-10-10
申请号:US15325434
申请日:2016-05-20
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Jing Feng
IPC: F21V8/00 , G02F1/1335 , G02F1/1343 , G09G3/20 , G09G3/36
CPC classification number: G02B6/0055 , G02B26/001 , G02B26/02 , G02F1/01 , G02F1/133512 , G02F1/134309 , G02F1/13439 , G09G3/2007 , G09G3/2011 , G09G3/3433 , G09G3/3611 , G09G2300/0426 , G09G2320/0271
Abstract: The present application discloses a display substrate including a base substrate; and a plurality of pixels on the base substrate. Each of the plurality of pixels in the display substrate includes a color generating layer on the base substrate; a first reflective layer surrounding at least one side of the color generating layer in plan view of the base substrate; and a second reflective layer having a light transmissive area and a light reflective area, the light transmissive area spaced apart from the first reflective layer in a direction perpendicular to the base substrate, the light reflective area configured to be spaced apart from the color generating layer in the direction perpendicular to the base substrate by an adjustable distance relative to the color generating layer. The first reflective layer is configured to reflect an incident light transmitted through the light transmissive area to the light reflective area, the light reflective area and the color generating layer are configured to direct the incident light reflected by the first reflective layer in a direction so that it may pass through the color generating layer.
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公开(公告)号:US11328652B2
公开(公告)日:2022-05-10
申请号:US16650306
申请日:2019-03-28
Inventor: Peng Liu , Bailing Liu , Fuqiang Li , Zhichong Wang , Jing Feng , Xinglong Luan
IPC: G09G5/00 , G09G3/20 , G11C19/28 , G09G3/3266 , G09G3/36
Abstract: A gate driving unit, a gate driving method, a gate driving circuit, a display panel and a display device are provided. The gate driving unit includes a start terminal, a first gate driving signal output terminal, a second gate driving signal output terminal, a pull-up control node control circuit, a pull-up node control circuit, configured to control a potential of a first pull-up node and a potential of a second pull-up node based on the potential of the pull-up control node, a first gate driving signal output circuit, a second gate driving signal output circuit, and a pull-down node control circuit, configured to control and maintain the potential of the pull-down node under the control of a third clock signal and a fourth clock signal, and control to reset the potential of the pull-down node under the control of the potential of the pull-up control node.
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公开(公告)号:US11308838B2
公开(公告)日:2022-04-19
申请号:US17051738
申请日:2020-01-21
Inventor: Zhichong Wang , Fuqiang Li , Jing Feng , Peng Liu , Xinglong Luan
Abstract: A shift register includes a first transistor, a second transistor, a pull-up node and a switch sub-circuit. A control electrode of the first transistor is connected to a signal input terminal, a first electrode of the first transistor is connected to a first voltage terminal, and a second electrode of the first transistor is connected to a first control node. A control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second voltage terminal, and a second electrode of the second transistor is connected to the first control node. The switching sub-circuit is connected to the first control node and the pull-up node, and is configured to control a line between the first control node and the pull-up node to be closed and opened.
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公开(公告)号:US20210209988A1
公开(公告)日:2021-07-08
申请号:US16769910
申请日:2020-01-08
Inventor: Zhichong Wang , Fuqiang Li , Peng Liu , Jing Feng , Xinglong Luan
Abstract: The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes an input sub-circuit, a discharging control sub-circuit, a discharging sub-circuit, and an output sub-circuit. The input sub-circuit is configured to transmit an input signal at an input signal terminal to a first node under control of a voltage at a second node. The discharging control sub-circuit is configured to transmit a first clock signal at a first clock signal terminal to the second node under control of a voltage at the first node. The discharging sub-circuit is configured to transmit a first constant voltage signal at a first constant voltage signal terminal to an output signal terminal under control of the voltage at the second node. The output sub-circuit is configured to transmit a second clock signal at a second clock signal terminal to the output signal terminal under control of the voltage at the first node.
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公开(公告)号:US10483129B2
公开(公告)日:2019-11-19
申请号:US15717527
申请日:2017-09-27
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jing Feng , Seung Jin Choi , Fangzhen Zhang , Wusheng Li , Zhijun Lv , Ce Ning , Jiushi Wang
IPC: H01L21/4763 , H01L21/027 , H01L29/66 , H01L29/786 , G03F7/00 , H01L27/12 , G03F7/38 , G03F7/20 , G03F7/40 , H01L21/321
Abstract: The disclosure discloses a method for roughening a surface of a metal layer, a thin film transistor, and a method for fabricating the same. The method for roughening the surface of a metal layer includes: forming a first photo-resist layer on the surface of the metal layer, and processing the first photo-resist layer at high temperature; and stripping the first photo-resist layer to roughen the surface of the metal layer.
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10.
公开(公告)号:US20180226269A1
公开(公告)日:2018-08-09
申请号:US15717527
申请日:2017-09-27
Applicant: BOE Technology Group Co., Ltd.
Inventor: Jing Feng , Seung Jin Choi , Fangzhen Zhang , Wusheng Li , Zhijun Lv , Ce Ning , Jiushi Wang
IPC: H01L21/4763 , H01L21/027 , H01L29/66 , H01L29/786 , H01L27/12 , G03F7/38 , G03F7/20 , G03F7/40 , G03F7/00
CPC classification number: H01L21/47635 , G03F7/0035 , G03F7/20 , G03F7/38 , G03F7/40 , H01L21/0274 , H01L21/321 , H01L27/1225 , H01L27/1288 , H01L29/66969 , H01L29/78618 , H01L29/7869
Abstract: The disclosure discloses a method for roughening a surface of a metal layer, a thin film transistor, and a method for fabricating the same. The method for roughening the surface of a metal layer includes: forming a first photo-resist layer on the surface of the metal layer, and processing the first photo-resist layer at high temperature; and stripping the first photo-resist layer to roughen the surface of the metal layer.
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