Digital exposure machine and exposure control method thereof

    公开(公告)号:US11971662B2

    公开(公告)日:2024-04-30

    申请号:US17083979

    申请日:2020-10-29

    IPC分类号: G03F7/00 G03F7/20 G03F7/22

    摘要: A digital exposure machine and an exposure control method thereof are disclosed. The exposure control method of the digital exposure machine includes: determining a scanning direction of the digital exposure machine, wherein a plurality of sub-pixels in an array include multiple rows of sub-pixels arranged in the scanning direction, the multiple rows of sub-pixels including a first row of sub-pixels in the scanning direction; determining a starting scanning position, the starting scanning position being located on an outer side of the first row of sub-pixels in the scanning direction; and performing a plurality of scannings to expose a display region of the first display substrate to be exposed, wherein a scanning pitch for each of the plurality of scannings is integer times of a pitch of two adjacent rows of sub-pixels of the first display substrate in the scanning direction.

    Display device, pixel compensation circuit and driving method thereof

    公开(公告)号:US11189230B2

    公开(公告)日:2021-11-30

    申请号:US16768395

    申请日:2019-12-16

    IPC分类号: G09G3/3258

    摘要: A display device, a pixel compensation circuit and a driving method thereof are disclosed. The pixel compensation circuit includes: a driving transistor, an initialization circuit, a storage circuit, a first data writing circuit, a second data writing circuit, a compensation circuit and a light emitting control circuit. A first terminal of the storage circuit is coupled to the gate electrode of the drive transistor, and the first data writing circuit is configured to write a data signal to a second terminal of the storage circuit. The second data writing circuit is configured to change a potential of the second terminal of the storage circuit so that a potential of the first terminal of the storage circuit is associated with the data signal. The compensation circuit is configured to charge the first terminal of the storage circuit so that it is associated with a threshold voltage of the drive transistor.

    Shift register and driving method therefor, gate driver circuit and display apparatus

    公开(公告)号:US11308838B2

    公开(公告)日:2022-04-19

    申请号:US17051738

    申请日:2020-01-21

    IPC分类号: G09G3/20 G11C19/28

    摘要: A shift register includes a first transistor, a second transistor, a pull-up node and a switch sub-circuit. A control electrode of the first transistor is connected to a signal input terminal, a first electrode of the first transistor is connected to a first voltage terminal, and a second electrode of the first transistor is connected to a first control node. A control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second voltage terminal, and a second electrode of the second transistor is connected to the first control node. The switching sub-circuit is connected to the first control node and the pull-up node, and is configured to control a line between the first control node and the pull-up node to be closed and opened.

    SHIFT REGISTER UNIT AND METHOD FOR DRIVING THE SAME, GATE DRIVING CIRCUIT AND METHOD FOR DRIVING THE SAME, AND DISPLAY APPARATUS

    公开(公告)号:US20210209988A1

    公开(公告)日:2021-07-08

    申请号:US16769910

    申请日:2020-01-08

    IPC分类号: G09G3/20 G11C19/28

    摘要: The present disclosure provides a shift register unit and a method for driving the same, a gate driving circuit and a method for driving the same, and a display apparatus. The shift register unit includes an input sub-circuit, a discharging control sub-circuit, a discharging sub-circuit, and an output sub-circuit. The input sub-circuit is configured to transmit an input signal at an input signal terminal to a first node under control of a voltage at a second node. The discharging control sub-circuit is configured to transmit a first clock signal at a first clock signal terminal to the second node under control of a voltage at the first node. The discharging sub-circuit is configured to transmit a first constant voltage signal at a first constant voltage signal terminal to an output signal terminal under control of the voltage at the second node. The output sub-circuit is configured to transmit a second clock signal at a second clock signal terminal to the output signal terminal under control of the voltage at the first node.

    Pixel circuit having a plurality of enable signals and gate signals in opposite phase and driving method thereof

    公开(公告)号:US11495178B2

    公开(公告)日:2022-11-08

    申请号:US17243915

    申请日:2021-04-29

    摘要: A pixel circuit includes a data writing sub-circuit, a light-emitting control sub-circuit and a driving sub-circuit. The data writing sub-circuit is connected to the driving sub-circuit, and is configured to write a data voltage signal into the driving sub-circuit and compensate it, in response to a first gate signal and a second gate signal. The light-emitting control sub-circuit is connected to the driving sub-circuit, and is configured to close a line between a first power supply voltage terminal and a second power supply voltage terminal, in response to a first enable signal and a second enable signal. The driving sub-circuit is configured to provide a driving current to a light-emitting device through the closed line according to the written data voltage signal. Phases of the first enable signal and the first gate signal are opposite, and phases of the second enable signal and the second gate signal are opposite.

    Gate driving unit, gate driving circuit, gate driving method and display device

    公开(公告)号:US11538385B2

    公开(公告)日:2022-12-27

    申请号:US17355858

    申请日:2021-06-23

    摘要: A gate driving unit includes: a pull-up node denoising circuit; a pull-down node control circuit; a pull-up node control circuit; and an energy storage circuit. The pull-up node denoising circuit is configured to, under control of a potential of the pull-down node, control coupling or discoupling between the first pull-up node and the input terminal. The pull-down node control circuit is configured to, under control of a control voltage, control the potential of the pull-down node; under control of a potential of the second pull-up node, control coupling or discoupling between the pull-down node and the input terminal. The pull-up node control circuit is configured to, under control of an anti-leakage control voltage, control coupling or discoupling between the first pull-up node and the second pull-up node, and configured to maintain the potential of the second pull-up node. The energy storage circuit is configured to store electric energy.