-
1.
公开(公告)号:US20170256631A1
公开(公告)日:2017-09-07
申请号:US15236696
申请日:2016-08-15
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Jian MIN , Xiaolong LI , Zhengyin XU , Ping SONG , Youwei WANG
IPC: H01L29/66 , H01L29/786 , H01L27/12 , H01L21/28 , H01L21/02 , H01L21/3105
CPC classification number: H01L29/66765 , H01L21/02532 , H01L21/02592 , H01L21/02675 , H01L21/28008 , H01L21/31053 , H01L27/1218 , H01L27/1229 , H01L27/1262 , H01L27/1296 , H01L29/42384 , H01L29/78618 , H01L29/78636 , H01L29/78678
Abstract: The present disclosure provides a TFT, its manufacturing method, an array substrate and a display device. The method includes steps of: forming a pattern of a gate electrode on a base substrate; forming a gate insulation layer with an even surface; forming a pattern of a polysilicon semiconductor layer; and forming patterns of a source electrode and a drain electrode. The step of forming the pattern of the polysilicon semiconductor layer includes: crystallizing the amorphous silicon layer, so as to form the polysilicon semiconductor layer.
-
公开(公告)号:US20220416189A1
公开(公告)日:2022-12-29
申请号:US17762049
申请日:2021-05-07
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Yang LIU , Zhengyin XU
Abstract: The present disclosure provides a display substrate, a manufacturing method thereof and a display panel. The display substrate includes a base substrate and a plurality of sub-pixels of different colors on the base substrate, wherein the plurality of sub-pixels include green sub-pixels, each of which includes an anode, a luminescent layer, and a cathode sequentially stacked in a direction away from the base substrate. The luminescent layer includes a first sub-layer, a second sub-layer and a third sub-layer sequentially stacked in the direction away from the base substrate; a molar ratio of P-type molecules to N-type molecules in a host material of the first sub-layer is greater than that of the second sub-layer, which in turn is greater than that of the third sub-layer.
-
3.
公开(公告)号:US20170200745A1
公开(公告)日:2017-07-13
申请号:US15393030
申请日:2016-12-28
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Jian MIN , Xiaolong LI , Zhengyin XU , Tao GAO , Dong LI , Shuai ZHANG
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1222 , H01L27/127 , H01L27/1288 , H01L29/78618 , H01L29/78675 , H01L29/78696
Abstract: A thin film transistor, a method for fabricating the same, an array substrate, and a display device are provided. The method comprises forming an active layer on a substrate, wherein source-and-drain-to-be-formed regions of the active layer are thicker than a semiconductor region between the source-and-drain-to-be-formed regions, and by a patterning process, forming a gate on the active layer, and forming a pattern of source and drain in the source-and-drain-to-be-formed regions of the active layer.
-
公开(公告)号:US20210165273A1
公开(公告)日:2021-06-03
申请号:US16072791
申请日:2017-12-15
Inventor: Wei Lin LAI , Guanyin WEN , Zhengyin XU , Chien Pang HUANG
IPC: G02F1/1335 , H01L27/32 , H01L51/52
Abstract: A display device includes a sub-pixel unit, the sub-pixel unit includes: a reflective liquid crystal display unit with a reflective display region, including a liquid crystal layer and a reflective layer; and a electroluminescent display unit with a light-emitting display region, wherein the light-emitting display region is overlapped with the reflective display region; wherein the reflective layer and the electroluminescent display unit are located on both sides of the liquid crystal layer respectively.
-
公开(公告)号:US20190206946A1
公开(公告)日:2019-07-04
申请号:US16045922
申请日:2018-07-26
Applicant: BOE Technology Group Co., Ltd.
Inventor: Zhengyin XU , Qingyun Bai
CPC classification number: H01L27/326 , H01L27/3246 , H01L27/3276 , H01L51/56 , H01L2227/323
Abstract: A display substrate, display device and manufacturing method of display substrate are provided. The display substrate includes: base substrate, and pixel defining pattern, heating circuit pattern, light-emitting layer and auxiliary light-emitting layer on one side of the base substrate. The pixel defining pattern has hollowed-out areas and bank disposed around hollowed-out areas where the light-emitting layer is located, and the auxiliary light-emitting layer at least partly covers the hollowed-out areas and area where the bank is located; the heating circuit pattern is on one side of the auxiliary light-emitting layer above the bank; and the auxiliary light-emitting layer includes first and second areas, orthographic projection of first area on the base substrate overlaps with orthographic projection of the hollowed-out areas on the base substrate, and orthographic projection of second area on the base substrate at least partly overlaps with orthographic projection of the heating circuit pattern on the base substrate.
-
6.
公开(公告)号:US20180331206A1
公开(公告)日:2018-11-15
申请号:US15543726
申请日:2016-07-25
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Jian MIN , Xiaolong LI , Tao GAO , Liangjian LI , Zhengyin XU
IPC: H01L29/66 , H01L21/02 , H01L21/027 , H01L21/30 , H01L29/36 , H01L29/786
CPC classification number: H01L29/66757 , H01L21/02532 , H01L21/02592 , H01L21/0262 , H01L21/02675 , H01L21/0272 , H01L21/0274 , H01L21/3003 , H01L27/1285 , H01L27/1288 , H01L29/36 , H01L29/78618 , H01L29/78675
Abstract: The present application discloses a method of fabricating a polycrystalline silicon thin film transistor, the method including forming an amorphous silicon layer on a base substrate having a pattern corresponding to a polycrystalline silicon active layer of the thin film transistor; the amorphous silicon layer having a first region corresponding to a source electrode and drain electrode contact region in the polycrystalline silicon active layer and a second region corresponding to a channel region in the polycrystalline silicon active layer; forming a first dopant layer on a side of the second region distal to the base substrate; forming a second dopant layer on a side of the first region distal to the base substrate; and crystallizing the amorphous silicon layer, the first dopant layer, and the second dopant layer to form the polycrystalline silicon active layer, the polycrystalline silicon active layer being doped with a dopant of the first dopant layer in the second region and doped with a dopant of the second dopant layer in the first region during the step of crystallizing the amorphous silicon layer.
-
-
-
-
-