公开(公告)号：US20140159038A1

公开(公告)日：2014-06-12

申请号：US14103175

申请日：2013-12-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jang Soon IM

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1251

Abstract: Provided are a CMOS circuit structure, a preparation method thereof and a display device, wherein a PMOS region in the CMOS circuit structure is of a LTPS TFT structure, that is, the PMOS semiconductor layer is prepared from a P type doped polysilicon material; an NMOS region is of an Oxide TFT structure, that is, the NMOS semiconductor layer is made of an oxide material; three doping processes applied to the NMOS region during the LTPS process may be omitted in the case in which the NMOS semiconductor layer in the NMOS region is made of an oxide material instead of the polysilicon material, which may simplify the preparation of the CMOS circuit structure as well as reduce a production cost. Furthermore, it is only required to crystallizing the PMOS semiconductor layer, which may also extend the lifespan of laser tube, contributing to reduction of the production cost.

Abstract translation: 提供了一种CMOS电路结构，其制备方法和显示装置，其中CMOS电路结构中的PMOS区域是LTPS TFT结构，即PMOS半导体层由P型掺杂多晶硅材料制备; NMOS区域是氧化物TFT结构，即NMOS半导体层由氧化物材料制成; 在NMOS区域中的NMOS半导体层由氧化物材料代替多晶硅材料制成的情况下，可以省略在LTPS工艺期间施加到NMOS区域的三种掺杂工艺，这可以简化CMOS电路结构的制备 并降低生产成本。 此外，仅需要使PMOS半导体层结晶，这也可能延长激光管的寿命，有助于降低生产成本。

公开(公告)号：US20160181289A1

公开(公告)日：2016-06-23

申请号：US14646416

申请日：2014-09-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping LONG ,  Zheng LIU ,  Zuqiang WANG ,  Jang Soon IM

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/32 ,  H01L29/66

CPC classification number: H01L27/1222 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2227/323

Abstract: An array substrate and manufacturing method thereof, a display device, a thin film transistor and manufacturing method thereof are provided. The manufacturing method of an array substrate includes forming an active material layer (501), a gate insulating layer (204) and a metal thin film (502) on a base substrate (201), and forming a pattern including an active layer (203) and a pattern including a gate electrode (205), a source electrode (206), a drain electrode (207), a gate line (1063) and a data line (1061) by a first patterning process; forming a passivation layer (301) on the base substrate (201), and forming a source contact hole (302), a drain contact hole (303), and an bridge-structure contact hole (1062a) by a second patterning process; forming a transparent conductive thin film (1401) on the base substrate (201), and removing the transparent conductive thin film (1404) partially, so that a source contact section (401), a drain contact section (402), a pixel electrode (403), and an bridge structure (1062) are formed. With the manufacturing method, the use number of patterning processes is decreased.

Abstract translation: 提供阵列基板及其制造方法，显示装置，薄膜​​晶体管及其制造方法。 阵列基板的制造方法包括在基底基板（201）上形成活性物质层（501），栅极绝缘层（204）和金属薄膜（502），形成包括活性层（203）的图案 ）和通过第一图案化工艺包括栅电极（205），源电极（206），漏电极（207），栅线（1063）和数据线（1061）的图案; 在所述基底基板上形成钝化层，通过第二构图工艺形成源极接触孔，漏极接触孔和桥接结构接触孔; 在所述基底基板上形成透明导电薄膜，将所述透明导电薄膜部分地去除，使得源极接触部分，漏极接触部分，像素电极， （403）和桥结构（1062）。 通过制造方法，图案化处理的使用次数减少。

公开(公告)号：US20150325602A1

公开(公告)日：2015-11-12

申请号：US14416358

申请日：2014-05-13

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jang Soon IM

IPC: H01L27/12

CPC classification number: H01L27/1251 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/127

Abstract: An array substrate and manufacturing method thereof and a display device are provided. The array substrate comprises a substrate (10) and a plurality of complementary thin film transistors provided on the substrate (10). The plurality of complementary thin film transistors comprise a first N-type thin film transistor (11) and a second P-type thin film transistor (12), and the first thin film transistor (11) is an oxide thin film transistor and the second thin film transistor (12) is a poly-silicon thin film transistor. The method of manufacturing the array substrate simplifies the manufacturing process and reduces production difficulty and cost.

Abstract translation: 提供阵列基板及其制造方法和显示装置。 阵列基板包括衬底（10）和设置在衬底（10）上的多个互补薄膜晶体管。 多个互补薄膜晶体管包括第一N型薄膜晶体管（11）和第二P型薄膜晶体管（12），第一薄膜晶体管（11）是氧化物薄膜晶体管，第二薄膜晶体管 薄膜晶体管（12）是多晶硅薄膜晶体管。 阵列基板的制造方法简化了制造工序，降低了生产难度和成本。

公开(公告)号：US20160300866A1

公开(公告)日：2016-10-13

申请号：US14436563

申请日：2014-09-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chunping LONG ,  Jang Soon IM ,  Chien Hung LIU

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1343 ,  H01L27/32 ,  G02F1/1368

CPC classification number: H01L27/1288 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13625 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

Abstract: An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion, a pixel electrode and a bridge structure.

Abstract translation: 公开了阵列基板及其制造方法，显示装置，薄膜​​晶体管（TFT）及其制造方法。 TFT的制造方法包括：在基板上形成有源层的图形和设置有金属膜的栅极绝缘层，通过一个图案化工艺图案化金属膜，形成栅电极，源电极， 漏电极，栅极线和数据线; 在基底基板上形成钝化层; 通过一个图案化工艺图案化钝化层，并形成源极接触孔，漏极接触孔和桥接结构接触孔; 在基底基板上形成透明导电膜，除去部分透明导电膜，形成源极接触部，漏极接触部，像素电极和桥接结构。

公开(公告)号：US20160013212A1

公开(公告)日：2016-01-14

申请号：US14428832

申请日：2014-06-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jang Soon IM

IPC: H01L27/12

Abstract: A complementary thin film transistor drive back-plate and manufacturing method thereof, a display panel. The method comprises: providing a lower semiconductor layer on a base substrate (101), and forming a P-type semiconductor active layer (103); providing a gate insulating layer (107) on the lower semiconductor layer; providing a lower electrode layer on the gate insulating layer (107), and forming a P-type transistor gate electrode (108), an N-type transistor source electrode (109) and an N-type transistor drain electrode (110); providing an upper semiconductor layer on the lower electrode layer, and foaming a pixel electrode (111) and an N-type semiconductor active layer (112); providing an isolation insulating protective layer (113) on the upper semiconductor layer, and forming contact holes (114) and a protection unit (115); providing an upper electrode layer on the isolation insulating protective layer (113), and aiming a P-type transistor source electrode (116), a P-type transistor drain electrode (117) and an N-type transistor gate electrode (118); and providing a pixel defining layer (119) on the upper electrode layer, and forming a pixel connection opening (120).

Abstract translation: 互补薄膜晶体管驱动背板及其制造方法，显示面板。 该方法包括：在基底（101）上提供下半导体层，形成P型半导体活性层（103）; 在所述下半导体层上提供栅极绝缘层（107）; 在栅极绝缘层（107）上形成下电极层，形成P型晶体管栅极（108），N型晶体管源电极（109）和N型晶体管漏电极（110）。 在下电极层上形成上半导体层，使像素电极（111）和N型半导体活性层（112）发泡; 在所述上半导体层上提供隔离绝缘保护层（113），以及形成接触孔（114）和保护单元（115）。 在隔离绝缘保护层（113）上设置上电极层，并对准P型晶体管源电极（116），P型晶体管漏电极（117）和N型晶体管栅电极（118）。 以及在所述上电极层上提供像素限定层（119），以及形成像素连接孔（120）。

公开(公告)号：US20160268139A1

公开(公告)日：2016-09-15

申请号：US14402872

申请日：2014-05-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng LIU ,  Jang Soon IM

IPC: H01L21/311 ,  H01L29/66 ,  H01J37/32 ,  H01L21/66

CPC classification number: H01L21/31116 ,  H01J37/32082 ,  H01J37/32935 ,  H01J37/32972 ,  H01J2237/334 ,  H01J2237/3343 ,  H01L22/12 ,  H01L22/26 ,  H01L29/66757 ,  H01L29/66765

Abstract: A method for manufacturing an array substrate, a film-etching monitoring and a film-etching monitoring device. The monitoring method comprises: monitoring and recording the transmittance reference value of a film after a film pattern is formed; and monitoring the transmittance present value of the film in real time in the process of etching an overcoating layer to form a through hole after the overcoating layer is formed on the film pattern, and monitoring the etching degree of the film by determining the variation between the transmittance present value and the transmittance reference value. The device comprises a plurality of light sources (3) and a plurality of light-sensitive probes (4) disposed in the chamber. The light sources (3) are configured to irradiate the film on a substrate; and the light-sensitive probes (4) are configured to sense the transmittance of the film.

Abstract translation: 阵列基板的制造方法，薄膜蚀刻监视和薄膜蚀刻监视装置。 监测方法包括：在形成膜图案之后监测和记录膜的透射率参考值; 并且在外涂层形成在膜图案上之后，在蚀刻外涂层的过程中实时监测膜的透射率现值，并通过确定膜的蚀刻程度来监测膜的蚀刻程度 透射率现值和透射率参考值。 该装置包括设置在腔室中的多个光源（3）和多个光敏探针（4）。 光源（3）构造成将膜照射在基板上; 并且感光探针（4）构造成感测膜的透射率。

公开(公告)号：US20150310807A1

公开(公告)日：2015-10-29

申请号：US14382506

申请日：2013-12-05

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Liang SUN ,  Jang Soon IM ,  Lujiang HUANGFU

IPC: G09G3/32 ,  G09G5/10

CPC classification number: G09G3/3291 ,  G09G3/3208 ,  G09G3/3233 ,  G09G3/3258 ,  G09G5/10 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/028

Abstract: A pixel circuit, a display panel and a display apparatus are configured to raise the uniformity of a display brightness within a display area of the display panel. The pixel circuit comprises a driving sub-circuit (2), whose first terminal (A) is connected with a first reference voltage source (Vref1) via a power supply lead, and second terminal (B) is connected with a first terminal of a light emitting device (D1); a charging sub-circuit (1), whose an output terminal is connected with a third terminal (C) of the driving sub-circuit (2), which is configured to charge the driving sub-circuit (2) before the driving sub-circuit (2) drives the light emitting device (D1) to emit light; and a compensation sub-circuit, whose first terminal is connected with a second terminal of the light emitting device (D1), second terminal is connected with a second reference voltage source (Vref2), which is configured to compensate for a voltage drop on the power supply lead of a voltage which is provided to the driving sub-circuit from the first reference voltage source (Vref1), so that a driving current for driving the light emitting device (D1) to emit light is irrelative with an attenuation amount.

Abstract translation: 像素电路，显示面板和显示装置被配置为提高显示面板的显示区域内的显示亮度的均匀性。 像素电路包括驱动子电路（2），其第一端子（A）经由电源引线与第一参考电压源（Vref1）连接，第二端子（B）与第一端子 发光装置（D1）; 充电子电路（1），其输出端子与驱动子电路（2）的第三端子（C）连接，其被配置为在驱动子电路（2）的驱动子电路 电路（2）驱动发光器件（D1）发光; 以及补偿子电路，其第一端子与发光器件（D1）的第二端子连接，第二端子与第二参考电压源（Vref2）连接，所述第二参考电压源被配置为补偿所述发光器件 提供从第一参考电压源（Vref1）提供给驱动子电路的电压的电源引线，使得用于驱动发光器件（D1）发光的驱动电流与衰减量无关。