公开(公告)号：US10937481B1

公开(公告)日：2021-03-02

申请号：US16534942

申请日：2019-08-07

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Peixuan Tan

IPC分类号： G11C5/06 ,  G11C7/18 ,  G11C7/10 ,  G11C11/16 ,  G11C11/419 ,  G11C11/418

摘要： Various implementations described herein are directed to a device having memory circuitry having bitcells coupled together via bitlines. The device may include polarity swapping circuitry having multiple conductive paths that are configured to couple the bitlines together. In some instances, first paths of the multiple conductive paths couple the bitlines together via first passgates, and second paths of the multiple conductive paths couple the bitlines together via second passgates.

公开(公告)号：US20210043241A1

公开(公告)日：2021-02-11

申请号：US16534942

申请日：2019-08-07

申请人： Arm Limited

发明人： Andy Wangkun Chen ,  Peixuan Tan

IPC分类号： G11C11/16 ,  G11C11/418 ,  G11C11/419

摘要： Various implementations described herein are directed to a device having memory circuitry having bitcells coupled together via bitlines. The device may include polarity swapping circuitry having multiple conductive paths that are configured to couple the bitlines together. In some instances, first paths of the multiple conductive paths couple the bitlines together via first passgates, and second paths of the multiple conductive paths couple the bitlines together via second passgates.

公开(公告)号：US10741227B2

公开(公告)日：2020-08-11

申请号：US16058375

申请日：2018-08-08

申请人： Arm Limited

发明人： Kumaraswamy Ramanathan ,  Peixuan Tan ,  Andy Wangkun Chen

IPC分类号： G11C8/00 ,  G11C7/22 ,  H03K3/037

摘要： Various implementations described herein refer to an integrated circuit having a first pulse generator and a second pulse generator. The first pulse generator generates a first clock pulse for a two pulse sequence based on one or more input signals. The second pulse generator is coupled to the first pulse generator and generates a second clock pulse for the two pulse sequence based on the one or more input signals. The second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.

公开(公告)号：US20200051602A1

公开(公告)日：2020-02-13

申请号：US16058375

申请日：2018-08-08

申请人： Arm Limited

发明人： Kumaraswamy Ramanathan ,  Peixuan Tan ,  Andy Wangkun Chen

IPC分类号： G11C7/22 ,  H03K3/037

摘要： Various implementations described herein refer to an integrated circuit having a first pulse generator and a second pulse generator. The first pulse generator generates a first clock pulse for a two pulse sequence based on one or more input signals. The second pulse generator is coupled to the first pulse generator and generates a second clock pulse for the two pulse sequence based on the one or more input signals. The second pulse generator has a single stack clock driver that provides an output clock signal having the two pulse sequence.