公开(公告)号：US20240411085A1

公开(公告)日：2024-12-12

申请号：US18208685

申请日：2023-06-12

Applicant: Applied Materials, Inc.

Inventor： Qintao ZHANG ,  Eric Jay SIMMONS ,  Mayrita ARRANDALE ,  Judeth Campbell SOUKUP ,  David J. LEE ,  Samphy HONG

IPC: G02B6/134 ,  C23C14/04 ,  C23C14/48 ,  C23C14/58 ,  G02B6/136

Abstract: Disclosed herein are approaches for adjusting local refractive index for photonics IC systems using selective waveguide ion implantation. In one approach, a method may include depositing an optical device film atop a base layer, patterning the optical device film into a plurality of sections, and implanting a first section of the plurality of sections of the optical device film to adjust a refractive index of the first section.

公开(公告)号：US20240405079A1

公开(公告)日：2024-12-05

申请号：US18327051

申请日：2023-05-31

Applicant: Applied Materials, Inc.

Inventor： Qintao ZHANG ,  Michel KHOURY

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: Disclosed herein are approaches for creating high electron mobility transistors with reduced contact resistance. In one approach, a method of forming a semiconductor device may include applying a first patterned mask on top of layered stack, wherein the layered stack includes a substrate, a buffer layer disposed over the substrate, a channel layer disposed above the buffer layer, and a barrier layer disposed above the channel layer. The method may further include forming, through an opening of the patterned mask, a source/drain contact in the barrier layer by delivering a first implant to the layered stack, and performing an etch process to form a contact opening in the source/drain contact. The method may further include performing a second implant to the source/drain contact, wherein the second implant is directed into the contact opening.

公开(公告)号：US20250038000A1

公开(公告)日：2025-01-30

申请号：US18227286

申请日：2023-07-27

Applicant: Applied Materials, Inc.

Inventor： Qintao ZHANG ,  Ludovico MEGALINI ,  Wei ZOU ,  Hans-Joachim L. GOSSMANN ,  William O. CHARLES

IPC: H01L21/04 ,  H01L21/266 ,  H01L21/306 ,  H01L29/40

Abstract: Disclosed herein are methods for forming MOSFET trenches with improved corner properties. In some embodiments, a method may include providing a device structure including an epitaxial layer and a hard mask over the epitaxial layer, and forming a trench through the well and the epitaxial layer, wherein the trench is defined by a sidewall, a bottom, and a corner at an intersection of the sidewall and the bottom. The method may further include implanting the device structure by delivering ions into the corner and into the bottom of the trench, and etching the trench to increase rounding of the corner.

公开(公告)号：US20220238674A1

公开(公告)日：2022-07-28

申请号：US17155662

申请日：2021-01-22

Applicant: Applied Materials, Inc.

Inventor： Qintao ZHANG ,  Samphy HONG ,  Lei ZHONG ,  David Jon LEE ,  Felix LEVITOV ,  Carlos CABALLERO ,  Durgaprasad CHATURVEDULA

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming a gate of a planar metal oxide semiconductor field effect transistor (MOSFET) reduces gate-drain capacitance. The method may include forming a first gate dielectric portion of the planar MOSFET with a first thickness that is configured to reduce the gate-drain capacitance of the planar MOSFET, forming a second gate dielectric portion of the planar MOSFET on the substrate with a second thickness less than the first thickness, and forming the gate of the planar MOSFET on the first gate dielectric portion and the second gate dielectric portion on the substrate.