公开(公告)号：US20190213166A1

公开(公告)日：2019-07-11

申请号：US15865638

申请日：2018-01-09

Applicant: Apple Inc.

Inventor： VLADISLAV PETKOV ,  SAURABH GARG ,  KARAN SANGHI ,  HAINING ZHANG

IPC: G06F15/17 ,  H04W4/80 ,  G06F13/42

Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

公开(公告)号：US20180129261A1

公开(公告)日：2018-05-10

申请号：US15647088

申请日：2017-07-11

Applicant: Apple Inc.

Inventor： SAURABH GARG ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/32 ,  G06F9/30

CPC classification number: G06F1/325 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F9/3004 ,  G06F9/4411 ,  G06F9/4418 ,  G06F13/404 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4278 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/44

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.