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    PROCESSING OF ASYMMETRICALLY QUANTIZED INPUT AND KERNEL COEFFICIENTS IN NEURAL NETWORK PROCESSOR
    1.
    发明公开
    PROCESSING OF ASYMMETRICALLY QUANTIZED INPUT AND KERNEL COEFFICIENTS IN NEURAL NETWORK PROCESSOR 审中-公开

    公开(公告)号：US20240329929A1

    公开(公告)日：2024-10-03

    申请号：US18127528

    申请日：2023-03-28

    Applicant: Apple Inc.

    Inventor： Lei Wang ,  Kenneth W. Waters ,  Michael L. Liu ,  Ji Liang Song ,  Youchang Kim

    IPC: G06F7/523 ,  G06F7/50

    CPC classification number: G06F7/523 ,  G06F7/50

    Abstract: Embodiments relate to performing multiply-accumulator operation on asymmetrically quantized input data and kernel data in a neural processor. Instead of adjusting to the input data at a multiply-accumulator to account for the asymmetric quantization of the input data, an adjusted bias for the multiply-accumulator operation is computed beforehand and stored in the multiply-accumulator. On the other hand, kernel coefficients derived from the kernel data are adjusted at the multiply-accumulator to account for the asymmetric quantization. In this way, computational complexity associated with asymmetric quantization may be reduced while increasing the efficiency of the convolution operations at the neural processor.

    NEURAL ENGINE WITH ACCELERATED MULTIPILER-ACCUMULATOR FOR CONVOLUTION OF INTERGERS
    2.
    发明公开
    NEURAL ENGINE WITH ACCELERATED MULTIPILER-ACCUMULATOR FOR CONVOLUTION OF INTERGERS 审中-公开

    公开(公告)号：US20240329933A1

    公开(公告)日：2024-10-03

    申请号：US18127650

    申请日：2023-03-28

    Applicant: Apple Inc.

    Inventor： Lei Wang ,  Jaewon Shin ,  Seungjin Lee ,  Ji Liang Song ,  Michael L. Liu ,  Christopher L. Mills

    IPC: G06F7/544 ,  G06N3/063

    CPC classification number: G06F7/5443 ,  G06N3/063

    Abstract: Embodiments of the present disclosure relate to a multiply-accumulator circuit that includes a main multiplier circuit operable in a floating-point mode or an integer mode and a supplemental multiplier circuit that operates in the integer mode. The main multiplier circuit generates a multiplied output that undergoes subsequent operations including a shifting operation in the floating-point mode whereas the supplemental multiplier generates another multiplied output that does not undergo any shifting operations. Hence, in the integer mode, two parallel multiply-add operations may be performed by the two multiplier circuits, and therefore accelerate the multiply-adder operations. Due to the lack of additional shifters associated with the supplemental multiplier circuit, the multiply-accumulator circuit does not have a significantly increased footprint.

    WI-FI Z-AXIS POSITIONING
    6.
    发明申请
    WI-FI Z-AXIS POSITIONING 有权

    公开(公告)号：US20210400615A1

    公开(公告)日：2021-12-23

    申请号：US17351900

    申请日：2021-06-18

    Applicant: Apple Inc.

    Inventor： Brian S. Smith ,  Robert W. Mayor ,  Wei Kong ,  Lei Wang

    IPC: H04W64/00 ,  H04B17/318

    Abstract: Described herein are techniques to enable a mobile device to determine a Z-axis coordinate based on altitudes associated with Wi-Fi access points detected in a Wi-Fi scan by the mobile device. One embodiment provides for an electronic device configured to compute a weighted average of Z-axis coordinates associated with detected Wi-Fi access points and determine a Z-axis coordinate for the electronic device based on the weighted average.

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