-
公开(公告)号：US07940102B2
公开(公告)日：2011-05-10
申请号：US12770793
申请日：2010-04-30
申请人： Alma Anderson , Joseph Rutkowski , Dave Oehler
发明人： Alma Anderson , Joseph Rutkowski , Dave Oehler
IPC分类号： H03K5/12
CPC分类号： H03K17/166
摘要： Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.
摘要翻译： 与示例实施例一致，用于I2C总线应用的边沿速率控制电路装置（300）包括响应于接收信号的状态转换的第一电路级（10，M1，M3）。 第二电路级（310,25,20,35,45,4H，M4，ESD）响应于接收信号的状态转换，并且包括响应于接收信号的状态转变而被激活的驱动电路（M4） 为了为I2C总线提供边沿转换信号，以及调节电路（310，R1，R2，M0，M2），适用于控制驱动电路并调节边沿转换信号的转换速率，转换速率更大 比第一电路级的接收信号的转换速率高大于最小值，小于指定用于在I2C总线上进行通信的最大转换速率。
-
公开(公告)号：US20090066381A1
公开(公告)日：2009-03-12
申请号：US11816710
申请日：2006-02-24
申请人： Alma Anderson , Joseph Rutkowski , Dave Oehler
发明人： Alma Anderson , Joseph Rutkowski , Dave Oehler
IPC分类号： H03K5/01
CPC分类号： H03K17/166
摘要： In an I2C bus, an edge rate control for an output slows the falling edge of a signal. In an example embodiment, there is an edge rate control circuit for use in an I2C bus. The circuit comprises a resistor divider having a first terminal, a divider terminal, and a second terminal. There is a first NMOS transistor having a source, drain, and gate terminal and a first PMOS transistor having a source, drain, and gate terminal; the source terminals of the first NMOS and first PMOS transistors are coupled to one another; the drain terminal of the first PMOS transistor is coupled to the divider terminal of the resistor divider; the gate of the first PMOS transistor is coupled to the second terminal of the resistor divider; and the drain of the first NMOS transistor is coupled to ground.
摘要翻译： 在I2C总线中，输出的边沿速率控制会降低信号的下降沿。 在示例实施例中，存在用于I2C总线的边沿速率控制电路。 该电路包括具有第一端子，分压器端子和第二端子的电阻器分压器。 存在具有源极，漏极和栅极端子的第一NMOS晶体管和具有源极，漏极和栅极端子的第一PMOS晶体管; 第一NMOS和第一PMOS晶体管的源极端子彼此耦合; 第一PMOS晶体管的漏极端子耦合到电阻分压器的除法器端子; 第一PMOS晶体管的栅极耦合到电阻分压器的第二端; 并且第一NMOS晶体管的漏极耦合到地。
-
公开(公告)号：US07733142B2
公开(公告)日：2010-06-08
申请号：US11816710
申请日：2006-02-24
申请人： Alma Anderson , Joseph Rutkowski , Dave Oehler
发明人： Alma Anderson , Joseph Rutkowski , Dave Oehler
IPC分类号： H03K5/12
CPC分类号： H03K17/166
摘要： Consistent with an example embodiment, an edge-rate control circuit arrangement (300) for an I2C bus application comprises a first circuit stage (10, M1, M3), responsive to a state transition of a received signal. A second circuit stage (310, 25, 20, 35, 45, M4, ESD) is responsive to the state transition of the received signal and includes drive circuitry (M4) that is activated in response to the state transition of the received signal in order to provide an edge-transition signal for an I2C bus, and regulation circuitry (310, R1, R2, M0, M2) adapted to control the drive circuit and regulate a transition rate for the edge-transition signal, the transition rate being greater than a transition rate of the received signal at the first circuit stage and greater than a minimum and less than a maximum transition rate designated for communication on the I2C bus.
摘要翻译： 与示例实施例一致，用于I2C总线应用的边沿速率控制电路装置（300）包括响应于接收信号的状态转换的第一电路级（10，M1，M3）。 第二电路级（310,25,20,35,45,4H，M4，ESD）响应于接收信号的状态转换，并且包括响应于接收信号的状态转变而被激活的驱动电路（M4） 为了为I2C总线提供边沿转换信号，以及调节电路（310，R1，R2，M0，M2），适用于控制驱动电路并调节边沿转换信号的转换速率，转换速率更大 比第一电路级的接收信号的转换速率高大于最小值，小于指定用于在I2C总线上进行通信的最大转换速率。
-
公开(公告)号：US20100237919A1
公开(公告)日：2010-09-23
申请号：US12294982
申请日：2007-03-31
申请人： Joseph Rutkowski , Alma Anderson
发明人： Joseph Rutkowski , Alma Anderson
IPC分类号： H03K5/12
CPC分类号： H03K19/00361 , H03K17/166
摘要： Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.
摘要翻译： 使用各种布置和方法实现边缘速率控制电路和方法。 使用一种这样的方法，通过使用隔离开关（106）将反馈电容器（116）与晶体管（108）的栅极去耦合来控制总线的输出信号。 晶体管（108）用于控制输出信号。 使用使用开关（112）选择性地耦合到反馈电容器（116）的电荷分配电容器（114），从反馈电容器（116）去除预定量的电荷。 开关（112）响应于输出信号达到输出电压而被使能，并且响应于电荷分配电容器（114）达到参考电压而被禁用。
-
公开(公告)号：US07859314B2
公开(公告)日：2010-12-28
申请号：US12294982
申请日：2007-03-31
申请人： Joseph Rutkowski , Alma Anderson
发明人： Joseph Rutkowski , Alma Anderson
IPC分类号： H03B1/00
CPC分类号： H03K19/00361 , H03K17/166
摘要： Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor (116) from a gate of a transistor (108) using an isolation switch (106). The transistor (108) is used to control the output signal. A predetermined amount of charge is removed from the feedback capacitor (116) using a charge distribution capacitor (114) that is selectively coupled to the feedback capacitor (116) using a switch (112). The switch (112) is enabled in response to the output signal reaching an output voltage and disabled in response to the charge distribution capacitor (114) reaching a reference voltage.
摘要翻译： 使用各种布置和方法实现边缘速率控制电路和方法。 使用一种这样的方法，通过使用隔离开关（106）使反馈电容器（116）与晶体管（108）的栅极去耦合来控制总线的输出信号。 晶体管（108）用于控制输出信号。 使用使用开关（112）选择性地耦合到反馈电容器（116）的电荷分配电容器（114），从反馈电容器（116）去除预定量的电荷。 开关（112）响应于输出信号达到输出电压而被使能，并且响应于电荷分配电容器（114）达到参考电压而被禁用。
-
公开(公告)号：US07761637B2
公开(公告)日：2010-07-20
申请号：US11913061
申请日：2006-05-01
IPC分类号： G06F13/24
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate latched service requests. Methods for one or more slave devices to request service from a master device involve detecting a condition that asserts a request for service signal, at a common node independent from the serial data transfer bus, to a master device of the bus. The request for service is latched it, within the slave, such that the request for service remains asserted regardless of a change in the detected condition. The request for service is de-asserted in response to interrogation of the slave, using the serial data transfer bus, by the master device. Devices may be configured as general purpose Input/Output devices, CODEC arrangements, or other slave devices, and may conform to I2C and/or SMBus serial communication specifications.
摘要翻译： 与一个示例实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统包括锁存的服务请求。 用于从主设备请求服务的一个或多个从设备的方法涉及检测在与串行数据传输总线独立的公共节点向服务总线的主设备发出对服务信号的请求的条件。 服务请求在从机中被锁存，使得服务请求保持置位，而不管检测到的状况如何变化。 响应于由主设备使用串行数据传输总线询问从设备，服务请求被取消断言。 设备可以配置为通用输入/输出设备，CODEC布置或其他从设备，并且可以符合I2C和/或SMBus串行通信规范。
-
公开(公告)号：US20080252407A1
公开(公告)日：2008-10-16
申请号：US12088730
申请日：2006-10-04
申请人： Alma Anderson
发明人： Alma Anderson
CPC分类号： H01F17/0033 , H01F41/046 , H01L23/5227 , Y10T29/4902
摘要： According to one example embodiment, an inductive element is used for power-conversion applications. The inductive element includes a substrate (188) having a first metal layer (190) on the substrate having a thickness greater than one micrometer and arranged as a first set of adjacent non-intersecting conducting segments. There is a ferromagnetic-based body (192) located on the first metal layer that has a ferromagnetic inner core area. At least one other metal layer (198) is on the ferromagnetic-based body and arranged as a second set of adjacent non-intersecting conducting segments. A plurality of conductive vias (194) are located in the ferromagnetic-based body and are arranged to connect respective ones of the first set of adjacent non-intersecting conducting segments to respective ones of the second set of adjacent non-intersecting conducting segments therein providing a contiguous conductive wrap around the inner core area. Other example embodiments include layer thicknesses in excess of those used in normal semiconductor processing.
摘要翻译： 根据一个示例实施例，电感元件用于功率转换应用。 电感元件包括在衬底上具有大于1微米厚度的第一金属层（190）的衬底（188），并且被布置为第一组相邻的不相交的导电段。 位于第一金属层上的铁磁体（192）具有铁磁内芯区域。 至少一个其它金属层（198）位于铁磁体上并且被布置为第二组相邻的非相交导电段。 多个导电通孔（194）位于铁磁体中，并且被布置成将第一组相邻的不相交的导电段中的相应的第一组相邻的不相交的导电段相互连接， 围绕内芯区域的连续的导电包裹物。 其他示例性实施例包括超过在正常半导体处理中使用的层厚度的层厚度。
-
公开(公告)号：US5654858A
公开(公告)日：1997-08-05
申请号：US332621
申请日：1994-10-31
申请人： Brian C. Martin , Alma Anderson , Harold G. Hanson
发明人： Brian C. Martin , Alma Anderson , Harold G. Hanson
IPC分类号： H02H9/04 , H03K17/082 , H03K19/003 , H02H9/00
CPC分类号： H03K19/00315 , H03K17/0822 , H03K2217/0018
摘要： Output overvoltage protection circuitry for circuits operating at low voltages (e.g., 3 v) interfacing to a higher voltage operating circuit (e.g., 5 v bus). To prevent problems with a pull-up PMOS device at the output when the bus is pulled-up to the higher voltage, a voltage node is provided in the circuit which follows the output voltage or the low supply voltage, whichever is higher, and a sub-circuit is provided to generate logic signals indicating when the bus is pulled too high. The PMOS device is then shut-down to prevent damage to the circuit.
摘要翻译： 用于在较高电压工作电路（例如5 V总线）上连接的低电压（例如3 v）工作的电路的输出过压保护电路。 为了防止当总线上拉到较高电压时输出端上拉PMOS器件出现问题，电路中提供了一个电压节点，该电压节点靠近输出电压或低电源电压（以较高者为准），以及 提供子电路以产生指示总线被拉得太高的逻辑信号。 然后关闭PMOS器件以防止损坏电路。
-
公开(公告)号：US07990081B2
公开(公告)日：2011-08-02
申请号：US12294001
申请日：2007-03-20
申请人： Manoj Chandran , Alma Anderson
发明人： Manoj Chandran , Alma Anderson
CPC分类号： H05B33/086 , H05B33/0818 , Y02B20/346
摘要： Methods and apparatus for implementing and operating pulse width modulation based LED dimmer controllers are described. A synchronization protocol is used to allow control information for the dimmer operations to be transferred to the PWM dimmer control clock domain from an external clock domain, such that visual artifacts are prevented when the control information is updated. Control information may be transferred to the LED dimmer controller via an I2C serial bus, and the synchronization protocol waits for an I2C STOP condition before updating control information across clock domain boundaries. The leading and trailing edges of an asserted group dimmer control signal are generated such that the active portion of the group dimmer control signal overlaps the active portion of individual LED pulse width modulated control signals. In this way, the pulse width modulation of the individual LED control signals is not cut off, or reduced in width by the group dimmer signal.
摘要翻译： 描述了实现和操作基于脉宽调制的LED调光控制器的方法和装置。 同步协议用于允许调光器操作的控制信息从外部时钟域传送到PWM调光控制时钟域，使得当更新控制信息时可防止视觉伪像。 控制信息可以通过I2C串行总线传输到LED调光控制器，并且在更新时钟域边界之间的控制信息之前，同步协议等待I2C STOP条件。 生成断言组调光控制信号的前沿和后沿，使得组调光控制信号的有效部分与各个LED脉冲宽度调制控制信号的有效部分重叠。 以这种方式，各个LED控制信号的脉冲宽度调制不被切断，或者通过组调光信号减小宽度。
-
公开(公告)号：US07934034B2
公开(公告)日：2011-04-26
申请号：US12769677
申请日：2010-04-29
IPC分类号： G06F13/00
CPC分类号： G06F13/4291
摘要： Consistent with one example embodiment, communications systems, using a serial data transfer bus having a serial data line and a clock line used to implement a communications protocol, incorporate programmable loading of a logic value into parallel slave device registers. The communications system includes a slave device having two or more registers, each register having two or more bits, each register configured to load data therein received in accordance with the communications protocol over the data transfer bus in a first configuration, and to load a single logic value into the plurality of bits in a second configuration. A programmable configuration register is configured to be programmed, in accordance with the communications protocol over the data transfer bus, to select two or more of the registers for loading of the single logic value into the two or more of bits of the selected registers in the second configuration.
摘要翻译： 与一个示例实施例一致，使用具有串行数据线的串行数据传输总线和用于实现通信协议的时钟线的通信系统将逻辑值的可编程加载并入到并行从设备寄存器中。 通信系统包括具有两个或更多个寄存器的从设备，每个寄存器具有两个或多个位，每个寄存器被配置为在第一配置中通过数据传输总线加载根据通信协议接收的数据，并且加载单个 第二配置中的多个位的逻辑值。 可编程配置寄存器被配置为根据数据传输总线上的通信协议来编程，以选择两个或更多个用于将单个逻辑值加载到所选择的寄存器的两个或更多个位中的寄存器 第二配置。
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.022 秒)
