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    INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE
    2.
    发明申请
    INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE 有权
    输入/输出存储器映射单元和北桥

    公开(公告)号：US20150120978A1

    公开(公告)日：2015-04-30

    申请号：US14523705

    申请日：2014-10-24

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Maggie Chan ,  Vincent Cueva ,  Liang Chen ,  Anthony Asaro ,  Jimshed Mirza ,  Greggory D. Donley ,  Bryan Broussard ,  Benjamin Tsien ,  Yaniv Adiri

    IPC: G06F12/10 ,  G06F13/24 ,  G06F12/12

    CPC classification number: G06F12/1009 ,  G06F12/1045 ,  G06F12/12 ,  G06F2212/684

    Abstract: The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

    Abstract translation: 本发明通过新的原子测试[0]和OR和Mask来提供在硬件中的页表访问和脏位管理。 本发明还提供了一种使ACE能够进行CCI翻译的垫圈。 该垫片进一步提供了ACE和CCI之间的请求转换，针对受害者和探针冲突的死锁避免，ARM屏障处理和电源管理交互。 本发明还提供了一种用于ARM受害者/探测器碰撞处理的解决方案，其使统一的北桥陷入僵局。 这些解决方案包括一个专用的回写虚拟通道，使用4跳协议的IO请求的探测器和MCT中的WrBack重新排序能力，其中受害者通过数据通过请求时更新旧的请求。

    Providing interrupts from an input-output memory management unit to guest operating systems
    3.
    发明授权
    Providing interrupts from an input-output memory management unit to guest operating systems 有权

    公开(公告)号：US11042495B2

    公开(公告)日：2021-06-22

    申请号：US16578165

    申请日：2019-09-20

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

    IPC: G06F13/24 ,  G06F9/455 ,  G06F13/16

    Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

    Secured input/output resource protection
    4.
    发明授权
    Secured input/output resource protection 有权

    公开(公告)号：US10824349B1

    公开(公告)日：2020-11-03

    申请号：US16222334

    申请日：2018-12-17

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Maggie Chan ,  Philip Ng ,  David Kaplan

    IPC: G06F3/06 ,  G06F21/60 ,  G06F9/455 ,  H04L9/06

    Abstract: A processing system includes a plurality of input/output (I/O) devices representing a plurality of I/O resources. Each I/O resource has at least one corresponding memory mapped I/O (MMIO) address range. A trap handler detects a write request targeting a configuration space of an identified I/O resource of the plurality of I/O resources and, responsive to determining the identified I/O resource is a protected I/O resource, selectively blocks the write request from further processing by the processing system based on whether the write request would change an MMIO address decoding of the identified I/O resource.

    Providing Interrupts from an Input-Output Memory Management Unit to Guest Operating Systems
    8.
    发明申请
    Providing Interrupts from an Input-Output Memory Management Unit to Guest Operating Systems 有权

    公开(公告)号：US20210089480A1

    公开(公告)日：2021-03-25

    申请号：US16578165

    申请日：2019-09-20

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

    IPC: G06F13/24 ,  G06F13/16 ,  G06F9/455

    Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

    Direct memory access authorization in a processing system
    9.
    发明授权
    Direct memory access authorization in a processing system 有权

    公开(公告)号：US10176122B2

    公开(公告)日：2019-01-08

    申请号：US15297868

    申请日：2016-10-19

    Applicant: Advanced Micro Devices, Inc. ,  ATI TECHNOLOGIES ULC

    Inventor： David Kaplan ,  Maggie Chan ,  Philip Ng

    IPC: G06F11/30 ,  G06F12/14 ,  G06F3/06 ,  G06F9/455 ,  G06F13/28

    Abstract: A processor employs a hardware encryption module in the memory access path between an input/out device and memory to cryptographically isolate secure information. In some embodiments, the encryption module is located at a memory controller of the processor, and each memory access request provided to the memory controller includes VM tag value identifying the source of the memory access request. The VM tag is determined based on a requestor ID identifying the source of the memory access request. The encryption module performs encryption (for write accesses) or decryption (for read accesses) of the data associated with the memory access based on an encryption key associated with the VM tag.

    Domain identifier and device identifier translation by an input-output memory management unit
    10.
    发明授权
    Domain identifier and device identifier translation by an input-output memory management unit 有权

    公开(公告)号：US11494211B2

    公开(公告)日：2022-11-08

    申请号：US16390663

    申请日：2019-04-22

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

    IPC: G06F9/455 ,  G06F12/1009

    Abstract: An electronic device includes a processor that executes a guest operating system and a hypervisor, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU handles communications between the IOMMU and the guest operating system by: replacing, in communications received from the guest operating system, guest domain identifiers (domainIDs) with corresponding host domainIDs and/or guest device identifiers (deviceIDs) with corresponding host deviceIDs before further processing the communications; replacing, in communications received from the IO device, host deviceIDs with guest deviceIDs before providing the communications to the guest operating system; and placing, into communications generated in the IOMMU and destined for the guest operating system, guest domainIDs and/or guest deviceIDs before providing the communications to the guest operating system. The IOMMU handles the communications without intervention by the hypervisor.

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