Invention Grant
- Patent Title: Input/output memory map unit and northbridge
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Application No.: US14523705Application Date: 2014-10-24
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Publication No.: US10025721B2Publication Date: 2018-07-17
- Inventor: Vydhyanathan Kalyanasundharam , Philip Ng , Maggie Chan , Vincent Cueva , Anthony Asaro , Jimshed Mirza , Greggory D. Donley , Bryan Broussard , Benjamin Tsien , Yaniv Adiri
- Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
- Applicant Address: US CA Sunnyvale CA Markham, Ontario
- Assignee: Advanced Micro Devices, Inc.,ATI Technologies ULC
- Current Assignee: Advanced Micro Devices, Inc.,ATI Technologies ULC
- Current Assignee Address: US CA Sunnyvale CA Markham, Ontario
- Agency: Volpe and Koenig, P.C.
- Main IPC: G06F12/10
- IPC: G06F12/10 ; G06F12/12 ; G06F12/1009 ; G06F12/1045 ; G06F13/38
Abstract:
The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.
Public/Granted literature
- US20150120978A1 INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE Public/Granted day:2015-04-30
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