公开(公告)号：US20250070031A1

公开(公告)日：2025-02-27

申请号：US18944757

申请日：2024-11-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H LOH ,  Raja SWAMINATHAN ,  Rahul AGARWAL ,  Brett P. WILKERSON

IPC: H01L23/538 ,  G05F1/575 ,  H01L25/065 ,  H01L27/06

Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

公开(公告)号：US20250149525A1

公开(公告)日：2025-05-08

申请号：US18615918

申请日：2024-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Alan D. SMITH ,  Raja SWAMINATHAN

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H10B80/00

Abstract: Disclosed herein are chip packages and electronic devices that utilized an active silicon bridge having a memory controller to interface between a logic device having at least one compute die and one or more memory stacks within a singular chip package. In one example, a chip package is provided that includes a substrate, a logic device, a memory stack, and an active silicon bridge. The logic device is disposed over the substrate. The logic device includes one or more compute dies. The memory stack is disposed over the substrate adjacent the logic device. The active silicon bridge has a first portion and a second portion. The first portion is disposed between the substrate and the logic device, while the second portion is disposed between the substrate and the memory stack.

公开(公告)号：US20240404897A1

公开(公告)日：2024-12-05

申请号：US18676665

申请日：2024-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Raja SWAMINATHAN ,  Mihir PANDYA ,  Liwei WANG ,  Samuel NAFFZIGER

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18

Abstract: A chip complex is provided that includes at least a first IC die present in a first common tier, a passive interposer, and a plurality of IC dies present in a second common tier. The passive interposer includes an interconnect formed in a back end of the line (BEOL) region. The first IC die present in the first common tier are hybrid bonded to a top side of the passive interposer. The plurality of IC dies present in the second common tier are also hybrid bonded to a bottom side of the passive interposer.

公开(公告)号：US20240371714A1

公开(公告)日：2024-11-07

申请号：US18644958

申请日：2024-04-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Raja SWAMINATHAN ,  Sri Ranga Sai BOYAPATI ,  Brett P. WILKERSON

IPC: H01L23/15 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A chip package having a package substrate including a top surface. A first chip module and a second chip module are mounted above the top surface of the package substrate. A first interposer is disposed between the package substrate and the first and second chip modules and includes a glass interposer. The first interposer couples the first and second chip modules to the package substrate. An interconnect bridge is disposed in a cavity of the glass interposer. The interconnect bridge includes circuitry that connects a circuitry of the first chip module to a circuitry of the second chip module.

公开(公告)号：US20240234304A1

公开(公告)日：2024-07-11

申请号：US18402688

申请日：2024-01-02

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Deepak Vasant KULKARNI ,  Samuel NAFFZIGER ,  Raja SWAMINATHAN ,  Matthew STRAAYER ,  Justin Michael BURKHART ,  Sri Ranga Sai BOYAPATI ,  Hemanth Kumar DHAVALESWARAPU ,  Alexander Helmut PFEIFFENBERGER ,  Manjunath D. HARITSA

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5227 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/29 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/29009 ,  H01L2224/29025 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/15311

Abstract: Chip packages are described herein that includes chiplets embedded in a core of a substrate of the chip package, such as a package substrate or an interposer. In one example, the chiplet includes voltage regulation circuitry that is coupled through a substrate core embedded inductor to an integrated circuit (IC) die mounted to the substrate.