公开(公告)号：US11081469B2

公开(公告)日：2021-08-03

申请号：US16580349

申请日：2019-09-24

Applicant: Arm Limited

Inventor： Saurabh Pijuskumar Sinha ,  Joel Thornton Irby ,  Supreet Jeloka

IPC: H01L23/367 ,  H01L25/065 ,  H01L21/66 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) can include a bottom tier with first circuitry and first backside TSVs coupled to a substrate; a top tier coupled to the first tier at a front side and having second circuitry and second backside TSVs; and a heat conductor on the second backside TSVs of the top tier. The heat conductor is coupled to the second backside TSVs to provide improved heat dissipation through the top tier. During pre-bond testing, the top tier can be tested at speed using the second backside TSVs.

公开(公告)号：US11468945B2

公开(公告)日：2022-10-11

申请号：US17071449

申请日：2020-10-15

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Joel Thornton Irby ,  Andy Wangkun Chen

IPC: G11C11/418 ,  G11C11/419

Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

公开(公告)号：US20220122655A1

公开(公告)日：2022-04-21

申请号：US17071449

申请日：2020-10-15

Applicant: Arm Limited

Inventor： Rahul Mathur ,  Mudit Bhargava ,  Joel Thornton Irby ,  Andy Wangkun Chen

IPC: G11C11/418 ,  G11C11/419

Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

公开(公告)号：US11520658B2

公开(公告)日：2022-12-06

申请号：US16669906

申请日：2019-10-31

Applicant: Arm Limited

Inventor： Joel Thornton Irby ,  Wendy Arnott Elsasser ,  Mudit Bhargava ,  Yew Keong Chong ,  George McNeil Lattimore ,  James Dennis Dodrill

IPC: G06F11/10 ,  G11C5/14 ,  G11C7/10 ,  G11C29/12 ,  G06N20/00

Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

公开(公告)号：US20210097173A1

公开(公告)日：2021-04-01

申请号：US16584865

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Joshua Randall ,  Joel Thornton Irby ,  Carl Wayne Vineyard ,  Mudit Bhargava

IPC: G06F21/55 ,  H03K19/003 ,  G11C13/00

Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

公开(公告)号：US11841943B2

公开(公告)日：2023-12-12

申请号：US16584865

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Joshua Randall ,  Joel Thornton Irby ,  Carl Wayne Vineyard ,  Mudit Bhargava

IPC: G06F21/55 ,  G11C13/00 ,  H03K19/003

CPC classification number: G06F21/554 ,  G11C13/004 ,  G11C13/0069 ,  H03K19/003 ,  G06F2221/034

Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

公开(公告)号：US10825745B1

公开(公告)日：2020-11-03

申请号：US16666816

申请日：2019-10-29

Applicant: Arm Limited

Inventor： Saurabh Pijuskumar Sinha ,  Xiaoqing Xu ,  Joel Thornton Irby ,  Mudit Bhargava

IPC: H01L21/66 ,  H01L25/18 ,  G06F30/30 ,  G06F30/333

Abstract: A multi-die integrated circuit with improved testability can include at least two dies that combined comprise an integrated circuit for a self-contained system, which includes logic and design-for-test features. The integrated circuit is split into at least two portions, where each portion is disposed on a corresponding one of the at least two dies. As part of the improved testability for both pre-bond testing of logic and post-bond testing of inter-die connections, at least one of the at least two dies further comprises a split-circuit-boundary scan chain. An automated design tool can be used to determine optimal ways for the integrated circuit for a self-contained system to be split into at least two portions for the corresponding at least two dies. In addition, a split-circuit-boundary scan chain option can be applied for each portion, via the automated design tool, to ensure boundary scans are available on timing paths.

公开(公告)号：US10761976B2

公开(公告)日：2020-09-01

申请号：US15361804

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Mudit Bhargava ,  Joel Thornton Irby ,  Vikas Chandra

IPC: H04L9/08 ,  G06F12/02 ,  G11C13/00

Abstract: A method and apparatus is provided for wear leveling of a storage medium in an electronic device. Wear leveling is achieved by mapping each logical memory address to a corresponding physical memory address. The mapping information is consistent over an on-period of a power cycle, but changes from one power cycle to another. The mapping information, such as a key value for example, may be stored in non-volatile memory such as, for example, a correlated electron random switch (CES) storage element. The mapping may be obtained by manipulating bits of the logical address to obtain the physical address.

公开(公告)号：US09953726B1

公开(公告)日：2018-04-24

申请号：US15361789

申请日：2016-11-28

Applicant: ARM Limited

Inventor： Joel Thornton Irby ,  Mudit Bhargava

IPC: G11C7/00 ,  G11C29/50 ,  G11C13/00

CPC classification number: G11C29/50008 ,  G11C13/0002 ,  G11C13/0069 ,  G11C13/0097

Abstract: An apparatus is provided for testing storage elements that include a variable impedance element switchable between a first impedance state and a second impedance state. The apparatus includes an interconnect circuit for coupling storage elements in a selected arrangement. The apparatus includes an impedance sensing circuit operable to measure at least a resistive component of an impedance of the coupled storage elements and a test controller operable to configure the interconnect circuit and initiate measurement of the combined impedance of the coupled storage elements by the impedance sensing circuit. The impedance sensing circuit compares the measured impedance with at least a resistive component of an expected impedance. The storage elements and apparatus may form part of an integrated circuit. A storage element may include a correlated electron switch, for example.

公开(公告)号：US09767924B1

公开(公告)日：2017-09-19

申请号：US15381415

申请日：2016-12-16

Applicant: ARM Limited

Inventor： Mudit Bhargava ,  Joel Thornton Irby

IPC: G11C29/26 ,  G11C29/00 ,  G11C8/10

CPC classification number: G11C29/76 ,  G11C29/028 ,  G11C29/4401 ,  G11C29/50

Abstract: An integrated circuit is provided for self-repair of a memory array. The circuit includes first word lines coupled to first memory rows of the memory array, one first word line for each bit of a line address word, second word lines coupled to one or more spare memory rows of the memory array. Repair configuration data is stored in memory cells within the integrated circuit to direct memory accesses to spare memory rows rather than dysfunctional first memory rows. A memory cell may be based on a correlated electron switch (CES). A built-in self-test circuit is provided to facilitate setting of repair configuration data. The repair data may be reconfigurable, enabling operating margins to be improved by testing under various operating conditions.