MULTILAYER PASSIVATION OR ETCH STOP TFT
    2.
    发明申请
    MULTILAYER PASSIVATION OR ETCH STOP TFT 有权
    多层钝化或蚀刻停止TFT

    公开(公告)号:US20160013320A1

    公开(公告)日:2016-01-14

    申请号:US14773209

    申请日:2014-03-04

    Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

    Abstract translation: 本发明一般涉及TFT和TFT的制造方法。 对于背沟道蚀刻TFT或蚀刻停止TFT,用于钝化层或蚀刻停止层的多个层允许在较不致密的背沟道保护层上形成非常密集的覆盖层。 封盖层可以是足够密实的,从而存在很少的针孔,因此氢不能通过半导体层。 因此,含氢前体可以用于覆盖层沉积。

    PIN HOLE EVALUATION METHOD OF DIELECTRIC FILMS FOR METAL OXIDE SEMICONDUCTOR TFT
    3.
    发明申请
    PIN HOLE EVALUATION METHOD OF DIELECTRIC FILMS FOR METAL OXIDE SEMICONDUCTOR TFT 有权
    用于金属氧化物半导体TFT的电介质膜的孔洞评估方法

    公开(公告)号:US20140273312A1

    公开(公告)日:2014-09-18

    申请号:US14199318

    申请日:2014-03-06

    CPC classification number: H01L22/12 H01L22/24

    Abstract: The present invention generally relates to methods measuring pinhole determination. In one aspect, a method of measuring pinholes in a stack, such as a TFT stack, is provided. The method can include forming an active layer on a deposition surface of a substrate, forming a dielectric layer over the active layer, delivering an etchant to at least the dielectric layer, to etch both the dielectric layer and any pinholes formed therein and optically measuring the pinhole density of the etched dielectric layer using the active layer.

    Abstract translation: 本发明一般涉及测量针孔确定的方法。 一方面,提供了一种测量堆叠中的针孔的方法,例如TFT堆叠。 该方法可以包括在衬底的沉积表面上形成有源层,在有源层上形成电介质层,向至少介电层递送蚀刻剂,以蚀刻电介质层和在其中形成的任何针孔,并光学测量 使用有源层的蚀刻介电层的针孔密度。

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