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公开(公告)号：US20240330205A1
公开(公告)日：2024-10-03
申请号：US18129305
申请日：2023-03-31
CPC分类号： G06F12/1408 , G06F21/72 , H04L9/14 , G06F2212/1052
摘要： A processing system includes one or more storage encryption circuits (SIECs) interconnected with one or more input/output (I/O) devices and a system memory. Each SIEC is configured to encrypt and decrypt data as the data passes between the I/O devices and the system memory. To this end, an SIEC includes slots each associated with respective memory addresses of the system memory. Each slot provides an aperture to the associated memory addresses such that the I/O devices use these apertures to indirectly target the associated memory addresses. As the data targeting the memory addresses associated with an aperture passes through an SIEC, the SIEC encrypts or decrypts the data using cryptographic keys stored on the SIEC.
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公开(公告)号：US12038847B2
公开(公告)日：2024-07-16
申请号：US17952933
申请日：2022-09-26
发明人： William A. Moyes
IPC分类号： G06F12/1009 , G06F12/0811
CPC分类号： G06F12/1009 , G06F12/0811
摘要： A/D bit storage, processing, and mode management techniques through use of a dense A/D bit representation are described. In one example, a memory management unit employs an A/D bit representation generation module to generate the dense A/D bit representation. In an implementation, the A/D bit representation is stored adjacent to existing page table structures of the multilevel page table hierarchy. In another example, memory management unit supports use of modes as part of A/D bit storage.
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公开(公告)号：US20240104023A1
公开(公告)日：2024-03-28
申请号：US17952933
申请日：2022-09-26
发明人： William A. Moyes
IPC分类号： G06F12/1009 , G06F12/0811
CPC分类号： G06F12/1009 , G06F12/0811
摘要： A/D bit storage, processing, and mode management techniques through use of a dense A/D bit representation are described. In one example, a memory management unit employs an A/D bit representation generation module to generate the dense A/D bit representation. In an implementation, the A/D bit representation is stored adjacent to existing page table structures of the multilevel page table hierarchy. In another example, memory management unit supports use of modes as part of A/D bit storage.
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公开(公告)号：US11816228B2
公开(公告)日：2023-11-14
申请号：US17032984
申请日：2020-09-25
CPC分类号： G06F21/602 , H04L9/14
摘要： Systems, apparatuses, and methods for implementing a metadata tweak for channel encryption differentiation are disclosed. A memory controller retrieves a device-unique identifier (ID) from a memory device coupled to a given memory channel slot. The memory controller uses the device-unique ID to generate a tweak value used for encrypting data stored in the device. In one scenario, the device-unique ID is embedded in the address bits of the tweak process. In this way, the memory device can be migrated to a different memory channel since the data can be decrypted independently of the channel. This is possible since the device-unique ID used for the tweak operation is retrieved from the metadata stored locally on the memory device. In one implementation, the memory device is a persistent dual in-line memory module (DIMM). In some implementations, the link between memory controller and memory device is a compute express link (CXL) compliant link.
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公开(公告)号：US11455251B2
公开(公告)日：2022-09-27
申请号：US17095229
申请日：2020-11-11
IPC分类号： G06F12/08 , G06F13/16 , G06F12/0804
摘要： A system-on-chip with runtime global push to persistence includes a data processor having a cache, an external memory interface, and a microsequencer. The external memory interface is coupled to the cache and is adapted to be coupled to an external memory. The cache provides data to the external memory interface for storage in the external memory. The microsequencer is coupled to the data processor. In response to a trigger signal, the microsequencer causes the cache to flush the data by sending the data to the external memory interface for transmission to the external memory.
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公开(公告)号：US20220147455A1
公开(公告)日：2022-05-12
申请号：US17095229
申请日：2020-11-11
IPC分类号： G06F12/0804 , G06F13/16
摘要： A system-on-chip with runtime global push to persistence includes a data processor having a cache, an external memory interface, and a microsequencer. The external memory interface is coupled to the cache and is adapted to be coupled to an external memory. The cache provides data to the external memory interface for storage in the external memory. The microsequencer is coupled to the data processor. In response to a trigger signal, the microsequencer causes the cache to flush the data by sending the data to the external memory interface for transmission to the external memory.
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公开(公告)号：US20220100870A1
公开(公告)日：2022-03-31
申请号：US17032984
申请日：2020-09-25
摘要： Systems, apparatuses, and methods for implementing a metadata tweak for channel encryption differentiation are disclosed. A memory controller retrieves a device-unique identifier (ID) from a memory device coupled to a given memory channel slot. The memory controller uses the device-unique ID to generate a tweak value used for encrypting data stored in the device. In one scenario, the device-unique ID is embedded in the address bits of the tweak process. In this way, the memory device can be migrated to a different memory channel since the data can be decrypted independently of the channel. This is possible since the device-unique ID used for the tweak operation is retrieved from the metadata stored locally on the memory device. In one implementation, the memory device is a persistent dual in-line memory module (DIMM). In some implementations, the link between memory controller and memory device is a compute express link (CXL) compliant link.
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