公开(公告)号：US20240321668A1

公开(公告)日：2024-09-26

申请号：US18474138

申请日：2023-09-25

Applicant: Advanced Micro Devices, Inc. ,  Xilinx, Inc.

Inventor： Thomas D. Burd ,  Gabriel H. Loh ,  John Wuu ,  Kevin Gillespie ,  Raja Swaminathan ,  Richard Schultz ,  Samuel Naffziger ,  Srividhya Venkataraman ,  Yan Wang

IPC: H01L23/34 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/34 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/80 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/16225 ,  H01L2224/32221 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1437

Abstract: A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20140181780A1

公开(公告)日：2014-06-26

申请号：US13725121

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas D. Burd ,  Srinivasaraghavan Srini Krishnamoorthy ,  Vishak K. Venkatraman ,  Yuri Apanovich ,  James A. Pistole ,  Rajit C. Chandra

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/76 ,  G06F2217/78 ,  G06F2217/80

Abstract: Methods and media for analyzing electrical designs are provided. A method includes and the media are configured for providing or loading to an analysis tool a design that includes a plurality of cell instances of a standard cell and estimating a failure rate of the design using in context electrical parameters for the plurality of cell instances and a parameterized electromigration (EM) view of the standard cell. Another method includes providing a standard cell of a standard cell library and characterizing the standard cell to create a parameterized thermal model to compute a temperature of an internal structure of the standard cell and a parameterized current model to compute a current through the internal structure of the standard cell given in context electrical parameters.

Abstract translation: 提供了分析电气设计的方法和介质。 方法包括并且介质被配置为向分析工具提供或加载包括标准单元的多个单元实例的设计，并且在多个单元实例的上下文电参数中估计设计的故障率，以及 标准电池的参数化电迁移（EM）视图。 另一种方法包括提供标准单元库的标准单元并表征标准单元以创建参数化热模型以计算标准单元的内部结构的温度和参数化的电流模型，以计算通过内部结构的电流 在上下文电参数中给出标准单元。

公开(公告)号：US20250167050A1

公开(公告)日：2025-05-22

申请号：US18751812

申请日：2024-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Srividhya Venkataraman ,  Ravinder Reddy Rachala ,  Samuel Naffziger ,  Thomas D. Burd ,  Phong T. Phan

IPC: H01L21/66

Abstract: A network of thermal sensors can be integrated within a semiconductor chip in a manner effective to provide local temperature monitoring and dynamic control of an associated device or system. The thermal sensors can include small area thermal ring oscillators located proximate to the core of a central processing unit (CPU), for example, and can be disposed on the chip at locations based on a designed output power density and attendant thermal gradients encountered during operation. In certain implementations, the presently-disclosed sensor configuration can be used to measure deviation from set threshold temperatures. Closed-loop control can be implemented to mitigate performance loss while adjusting the clock speed of the CPU independent of the system management unit.