公开(公告)号：US20140297961A1

公开(公告)日：2014-10-02

申请号：US13854724

申请日：2013-04-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mithuna Thottethodi ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0888 ,  G06F12/0893

Abstract: A cache memory receives a request to perform a write operation. The request specifies an address. A first determination is made that the cache memory does not include a cache line corresponding to the address. A second determination is made that the address is between a previous value of a stack pointer and a current value of the stack pointer. A third determination is made that a write history indicator is set to a specified value. The write operation is performed in the cache memory without waiting for a cache fill corresponding to the address to be performed, in response to the first, second, and third determinations.

Abstract translation: 缓存存储器接收执行写入操作的请求。 请求指定一个地址。 首先确定高速缓冲存储器不包括与该地址对应的高速缓存行。 第二个确定是地址在堆栈指针的先前值和堆栈指针的当前值之间。 第三个确定写入历史指示符被设置为指定值。 响应于第一，第二和第三确定，在高速缓冲存储器中执行写入操作，而不等待与要执行的地址相对应的高速缓存填充。

公开(公告)号：US09626428B2

公开(公告)日：2017-04-18

申请号：US14024139

申请日：2013-09-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna Thottethodi ,  Steven Reinhardt

IPC: G06F12/10 ,  G06F17/30

CPC classification number: G06F17/30628

Abstract: A system and method for accessing a hash table are provided. A hash table includes buckets where each bucket includes multiple chains. When a single instruction multiple data (SIMD) processor receives a group of threads configured to execute a key look-up instruction that accesses an element in the hash table, the threads executing on the SIMD processor identify a bucket that stores a key in the key look-up instruction. Once identified, the threads in the group traverse the multiple chains in the bucket, such that the elements at a chain level in the multiple chains are traversed in parallel. The traversal continues until a key look-up succeeds or fails.

公开(公告)号：US20140181411A1

公开(公告)日：2014-06-26

申请号：US13723294

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mithuna Thottethodi ,  Gabriel Loh ,  Mauricio Breternitz ,  James O'Connor ,  Yasuko Eckert

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F2212/601 ,  Y02D10/13

Abstract: A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented.

Abstract translation: 提供了一种数据处理装置，其包括工作存储器组和相关处理引擎的阵列。 工作存储器阵列配置有至少一个可独立激活的存储体。 脏数据计数器（DDC）与可独立激活的存储体相关联，并且被配置为反映从可独立激活的存储体选择性地去激活时从可独立激活的存储体组迁移的脏数据的计数。 DDC被配置为在与暂时状态相关联的可独立激活的存储体的重新激活时选择性地减少脏数据的计数。 在过渡状态下，处理引擎对重新激活的存储体的每个脏数据访问也相对于阵列的另一存储体进行。 在另一个存储体中发现脏数据的情况下，脏数据的计数减少。

公开(公告)号：US09128856B2

公开(公告)日：2015-09-08

申请号：US13854724

申请日：2013-04-01

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna Thottethodi ,  Yasuko Eckert ,  Srilatha Manne

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0888 ,  G06F12/0893

Abstract: A cache memory receives a request to perform a write operation. The request specifies an address. A first determination is made that the cache memory does not include a cache line corresponding to the address. A second determination is made that the address is between a previous value of a stack pointer and a current value of the stack pointer. A third determination is made that a write history indicator is set to a specified value. The write operation is performed in the cache memory without waiting for a cache fill corresponding to the address to be performed, in response to the first, second, and third determinations.

Abstract translation: 缓存存储器接收执行写入操作的请求。 请求指定一个地址。 首先确定高速缓冲存储器不包括与该地址对应的高速缓存行。 第二个确定是地址在堆栈指针的先前值和堆栈指针的当前值之间。 第三个确定写入历史指示符被设置为指定值。 响应于第一，第二和第三确定，在高速缓冲存储器中执行写入操作，而不等待与要执行的地址相对应的高速缓存填充。

公开(公告)号：US08935472B2

公开(公告)日：2015-01-13

申请号：US13723294

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna Thottethodi ,  Gabriel Loh ,  Mauricio Breternitz ,  James O'Connor ,  Yasuko Eckert

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F2212/601 ,  Y02D10/13

Abstract: A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented.

Abstract translation: 提供了一种数据处理装置，其包括工作存储器组和相关处理引擎的阵列。 工作存储器阵列配置有至少一个可独立激活的存储体。 脏数据计数器（DDC）与可独立激活的存储体相关联，并且被配置为反映从可独立激活的存储体选择性地去激活时从可独立激活的存储体组迁移的脏数据的计数。 DDC被配置为在与暂时状态相关联的可独立激活的存储体的重新激活时选择性地减少脏数据的计数。 在过渡状态下，处理引擎对重新激活的存储体的每个脏数据访问也相对于阵列的另一存储体进行。 在另一个存储体中发现脏数据的情况下，脏数据的计数减少。