公开(公告)号：US08935472B2

公开(公告)日：2015-01-13

申请号：US13723294

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Mithuna Thottethodi ,  Gabriel Loh ,  Mauricio Breternitz ,  James O'Connor ,  Yasuko Eckert

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F2212/601 ,  Y02D10/13

Abstract: A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented.

Abstract translation: 提供了一种数据处理装置，其包括工作存储器组和相关处理引擎的阵列。 工作存储器阵列配置有至少一个可独立激活的存储体。 脏数据计数器（DDC）与可独立激活的存储体相关联，并且被配置为反映从可独立激活的存储体选择性地去激活时从可独立激活的存储体组迁移的脏数据的计数。 DDC被配置为在与暂时状态相关联的可独立激活的存储体的重新激活时选择性地减少脏数据的计数。 在过渡状态下，处理引擎对重新激活的存储体的每个脏数据访问也相对于阵列的另一存储体进行。 在另一个存储体中发现脏数据的情况下，脏数据的计数减少。

公开(公告)号：US20140181411A1

公开(公告)日：2014-06-26

申请号：US13723294

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mithuna Thottethodi ,  Gabriel Loh ,  Mauricio Breternitz ,  James O'Connor ,  Yasuko Eckert

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F2212/601 ,  Y02D10/13

Abstract: A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented.

Abstract translation: 提供了一种数据处理装置，其包括工作存储器组和相关处理引擎的阵列。 工作存储器阵列配置有至少一个可独立激活的存储体。 脏数据计数器（DDC）与可独立激活的存储体相关联，并且被配置为反映从可独立激活的存储体选择性地去激活时从可独立激活的存储体组迁移的脏数据的计数。 DDC被配置为在与暂时状态相关联的可独立激活的存储体的重新激活时选择性地减少脏数据的计数。 在过渡状态下，处理引擎对重新激活的存储体的每个脏数据访问也相对于阵列的另一存储体进行。 在另一个存储体中发现脏数据的情况下，脏数据的计数减少。

公开(公告)号：US20140177347A1

公开(公告)日：2014-06-26

申请号：US13721315

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Niladrish Chatterjee ,  James O'Connor ,  Nuwan Jayasena ,  Gabriel Loh

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G11C2207/2236

Abstract: A method and apparatus for inter-row data transfer in memory devices is described. Data transfer from one physical location in a memory device to another is achieved without engaging the external input/output pins on the memory device. In an example method, a memory device is responsive to a row transfer (RT) command which includes a source row identifier and a target row identifier. The memory device activates a source row and storing source row data in a row buffer, latches the target row identifier into the memory device, activates a word line of a target row to prepare for a write operation, and stores the source row data from the row buffer into the target row.

Abstract translation: 描述了存储器件中行间数据传输的方法和装置。 从存储设备中的一个物理位置到另一物理位置的数据传输是在不将外部输入/输出引脚接入存储器件的情况下实现的。 在示例性方法中，存储器设备响应于包括源行标识符和目标行标识符的行传送（RT）命令。 存储器件激活源行并且将源行数据存储在行缓冲器中，将目标行标识符锁存到存储器件中，激活目标行的字线以准备写入操作，并存储源行数据 行缓冲区到目标行。

公开(公告)号：US20150261472A1

公开(公告)日：2015-09-17

申请号：US14728438

申请日：2015-06-02

Applicant: Advanced Micro Devices, Inc.

Inventor： James O'Connor ,  Warren Kruger

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1052 ,  G11C7/1006 ,  G11C7/1009 ,  G11C29/76 ,  G11C2029/0411

Abstract: A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.

Abstract translation: 提供了存储器和将数据存储在存储器中的方法。 存储器包括包括数据位和附加位的存储器块。 存储器包括逻辑，当接收到第一命令时，将数据写入存储器块的数据位，其中根据第一输入对数据进行掩蔽。 响应于第二命令的逻辑将数据写入存储器块的数据位，并将第二个输入写入存储器块的附加位。

公开(公告)号：US09064606B2

公开(公告)日：2015-06-23

申请号：US13722716

申请日：2012-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： James O'Connor ,  Warren Kruger

IPC: G11C7/10 ,  G11C29/00 ,  G06F11/10 ,  G11C29/04

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1052 ,  G11C7/1006 ,  G11C7/1009 ,  G11C29/76 ,  G11C2029/0411

Abstract: A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.

Abstract translation: 提供了存储器和将数据存储在存储器中的方法。 存储器包括包括数据位和附加位的存储器块。 存储器包括逻辑，当接收到第一命令时，将数据写入存储器块的数据位，其中根据第一输入对数据进行掩蔽。 响应于第二命令的逻辑将数据写入存储器块的数据位，并将第二个输入写入存储器块的附加位。

公开(公告)号：US09003130B2

公开(公告)日：2015-04-07

申请号：US13719730

申请日：2012-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： James O'Connor ,  Bradford M. Beckmann

IPC: G06F13/00 ,  G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0815

Abstract: A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated with a processing engine. In some embodiments, the cache is configured to store a plurality of cache entries where each cache entry includes a cache line configured to store data and a corresponding cache tag configured to store address information associated with data stored in the cache line. Such address information includes invalidation flags with respect to addresses stored in the cache tags. Each cache tag is associated with an invalidation tag configured to store information related to invalidation commands of addresses stored in the cache tag. In such embodiment, the cache is configured to set invalidation flags of cache tags based upon information stored in respective invalidation tags.

Abstract translation: 提供了一种有助于高速缓存一致性策略的数据处理设备。 在一个实施例中，数据处理设备利用与处理引擎相关联的高速缓存的无效标签。 在一些实施例中，高速缓存被配置为存储多个高速缓存条目，其中每个高速缓存条目包括被配置为存储数据的高速缓存行和被配置为存储与存储在高速缓存行中的数据相关联的地址信息的对应高速缓存标签。 这样的地址信息包括关于存储在高速缓存标签中的地址的无效标志。 每个缓存标签与被配置为存储与存储在高速缓存标签中的地址的无效命令相关的信息的无效标签相关联。 在这种实施例中，高速缓存被配置为基于存储在相应无效标签中的信息来设置高速缓存标签的无效标志。

公开(公告)号：US20140173210A1

公开(公告)日：2014-06-19

申请号：US13719730

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James O'Connor ,  Bradford M. Beckmann

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0815

Abstract: A data processing device is provided that facilitates cache coherence policies. In one embodiment, a data processing device utilizes invalidation tags in connection with a cache that is associated with a processing engine. In some embodiments, the cache is configured to store a plurality of cache entries where each cache entry includes a cache line configured to store data and a corresponding cache tag configured to store address information associated with data stored in the cache line. Such address information includes invalidation flags with respect to addresses stored in the cache tags. Each cache tag is associated with an invalidation tag configured to store information related to invalidation commands of addresses stored in the cache tag. In such embodiment, the cache is configured to set invalidation flags of cache tags based upon information stored in respective invalidation tags.

Abstract translation: 提供了一种有助于高速缓存一致性策略的数据处理设备。 在一个实施例中，数据处理设备利用与处理引擎相关联的高速缓存的无效标签。 在一些实施例中，高速缓存被配置为存储多个高速缓存条目，其中每个高速缓存条目包括被配置为存储数据的高速缓存行和被配置为存储与存储在高速缓存行中的数据相关联的地址信息的对应高速缓存标签。 这样的地址信息包括关于存储在高速缓存标签中的地址的无效标志。 每个缓存标签与被配置为存储与存储在高速缓存标签中的地址的无效命令相关的信息的无效标签相关联。 在这种实施例中，高速缓存被配置为基于存储在相应无效标签中的信息来设置高速缓存标签的无效标志。

公开(公告)号：US08880809B2

公开(公告)日：2014-11-04

申请号：US13663335

申请日：2012-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel Loh ,  James O'Connor

IPC: G06F13/00

CPC classification number: G06F11/3433 ,  G06F11/349 ,  G06F13/1663 ,  G06F2201/86 ,  G06F2201/88

Abstract: Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus contentions, row-buffer conflicts, and increased write-to-read turnaround time caused by a first core in the processor-based system that causes a delay in access to the memory by a second core in the processor-based system; deriving a control signal based on the number of interference events; and transmitting the control signal to one or more resources of the processor-based system to reduce the number of interference events from an original number of interference events.

Abstract translation: 描述了用于在基于处理器的系统中控制对存储器的访问的方法的实施例，包括监视多个干扰事件，例如银行争用，总线争用，行缓冲器冲突以及由 基于处理器的系统中的第一核心，其导致在基于处理器的系统中由第二核心访问存储器的延迟; 基于干扰事件的数量导出控制信号; 以及将所述控制信号发送到所述基于处理器的系统的一个或多个资源，以从原始数量的干扰事件减少干扰事件的数量。

公开(公告)号：US20140173225A1

公开(公告)日：2014-06-19

申请号：US13719710

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Niladrish Chatterjee ,  James O'Connor ,  Gabriel Loh ,  Nuwan Jayasena

IPC: G06F12/00

CPC classification number: G06F9/3887 ,  G06F9/3824

Abstract: Apparatus, computer readable medium, and method of servicing memory requests are presented. A first plurality of memory requests are associated together, wherein each of the first plurality of memory requests is generated by a corresponding one of a first plurality of processors, and wherein each of the first plurality of processors is executing a first same instruction. A second plurality of memory requests are associated together, wherein each of the second plurality of memory requests is generated by a corresponding one of a second plurality of processors, and wherein each of the second plurality of processors is executing a second same instruction. A determination is made to service the first plurality of memory requests before the second plurality of memory requests and the first plurality of memory requests is serviced before the second plurality of memory requests.

Abstract translation: 提供了设备，计算机可读介质和服务存储器请求的方法。 第一多个存储器请求被关联在一起，其中第一多个存储器请求中的每一个由第一多个处理器中的对应的一个处理器生成，并且其中第一多个处理器中的每一个正在执行第一个相同的指令。 第二多个存储器请求被关联在一起，其中第二多个存储器请求中的每一个由第二多个处理器中的对应的一个处理器生成，并且其中第二多个处理器中的每一个正在执行第二个相同的指令。 确定在第二多个存储器请求之前服务第一多个存储器请求，并且在第二多个存储器请求之前服务第一多个存储器请求。

公开(公告)号：US09436398B2

公开(公告)日：2016-09-06

申请号：US14728438

申请日：2015-06-02

Applicant: Advanced Micro Devices, Inc.

Inventor： James O'Connor ,  Warren Kruger

IPC: G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G11C29/00 ,  G11C29/04

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1052 ,  G11C7/1006 ,  G11C7/1009 ,  G11C29/76 ,  G11C2029/0411

Abstract: A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block.