公开(公告)号：US11177896B2

公开(公告)日：2021-11-16

申请号：US16655261

申请日：2019-10-17

Applicant: ACCTON TECHNOLOGY CORPORATION

Inventor： Bang-Jun Tai ,  Yu-Yun Lee

IPC: H04J3/06

Abstract: A time synchronization device performs a time synchronization process with a device that provides first and second time values. The time synchronization device includes a packet processing circuit, a time counting circuit, and a processor. The packet processing circuit includes a timestamp counter having an N-bit length, and the packet processing circuit provides first to third time counting values. The processor calculates the first offset value based on the first and second time values and the first and second time counting values; calculates the first adjustment value based on the first offset value and the reciprocal of the frequency of the time counting circuit; calculates a second quotient value and a second remainder value based on the first adjustment value and the N-bit length; and calculates the receiving time of the second synchronization packet based on the N-bit length, the second quotient value, and the third time counting value.

公开(公告)号：US09898022B2

公开(公告)日：2018-02-20

申请号：US14320621

申请日：2014-06-30

Applicant: ACCTON TECHNOLOGY CORPORATION

Inventor： Yu-Yun Lee ,  Jung-Hui Wei ,  Yi-Da Fan

IPC: G05F1/625 ,  H02J1/10

CPC classification number: G05F1/625 ,  H02J1/10 ,  Y10T307/549

Abstract: A power sharing device and method thereof are disclosed herein. The power sharing device includes a control unit, multiple regulators and multiple feedback circuits. Each regulator includes a first input terminal, a second input terminal and an output terminal. The control unit generates multiple pulse-width modulation signals. The first input terminal receives one of multiple input voltages. The second input terminal receives one of the pulse width modulation signals. The output terminal selectively outputs an output power. Each feedback circuit is coupled between the second input terminal and the output terminal of one of the regulators. The output terminals of the regulators are coupled to a load, and the regulators selectively output the output power one at a time and in rotation according to the input voltages and duty cycles of the pulse-width modulation signals.

公开(公告)号：US11664967B2

公开(公告)日：2023-05-30

申请号：US17444909

申请日：2021-08-11

Applicant: ACCTON TECHNOLOGY CORPORATION

Inventor： Bang-Jun Tai ,  Yu-Yun Lee

IPC: H04L7/00 ,  H04J3/06

CPC classification number: H04L7/0033 ,  H04J3/0667 ,  H04J3/0697 ,  H04L7/0091

Abstract: A network device adapted for sending a synchronization packet to a slave device. The synchronization packet includes a timestamp field and a correction field. The network device includes a counting circuit, a communication chip, and a processor. The counting circuit is configured to provide a calendar time TOD. The communication chip includes a first port, a second port, and a timestamp circuit which has a bit number N. The processor is coupled to the first port of the communication chip. The processor is configured to: obtain a remainder R according to the calendar time TOD and the bit number N; and write the calendar time TOD and the remainder R into the synchronization packet.

公开(公告)号：US09195627B2

公开(公告)日：2015-11-24

申请号：US13946048

申请日：2013-07-19

Applicant: ACCTON TECHNOLOGY CORPORATION

Inventor： Chi-Hsu Chen ,  Yi-Liang Yeh ,  Yu-Yun Lee ,  Yuan-Hsiung Sung ,  Kuo-Jui Yu

IPC: G06F1/04 ,  G06F13/42

CPC classification number: G06F1/04 ,  G06F1/08 ,  G06F13/4291

Abstract: An apparatus and a method of controlling clock signals for a master device and a slave device are disclosed. The controlling apparatus includes: a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; and a control module receiving a first clock signal from the master device via the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device via the second connection port; wherein when the first clock signal is switched from a first logic level to a second logic level, the control module controls the first connection port to maintain the second logic level in a time interval.

Abstract translation: 公开了一种用于控制主设备和从设备的时钟信号的设备和方法。 控制装置包括：耦合到主设备的第一时钟线的第一连接端口; 耦合到所述从设备的第二时钟线的第二连接端口; 以及控制模块，经由所述第一连接端口从所述主设备接收第一时钟信号，根据所述第一时钟信号产生第二时钟信号，并经由所述第二连接端口将所述第二时钟信号发送到所述从设备; 其中当所述第一时钟信号从第一逻辑电平切换到第二逻辑电平时，所述控制模块控制所述第一连接端口以在时间间隔内维持所述第二逻辑电平。