Time synchronization device and time synchronization method

    公开(公告)号:US11177896B2

    公开(公告)日:2021-11-16

    申请号:US16655261

    申请日:2019-10-17

    Abstract: A time synchronization device performs a time synchronization process with a device that provides first and second time values. The time synchronization device includes a packet processing circuit, a time counting circuit, and a processor. The packet processing circuit includes a timestamp counter having an N-bit length, and the packet processing circuit provides first to third time counting values. The processor calculates the first offset value based on the first and second time values and the first and second time counting values; calculates the first adjustment value based on the first offset value and the reciprocal of the frequency of the time counting circuit; calculates a second quotient value and a second remainder value based on the first adjustment value and the N-bit length; and calculates the receiving time of the second synchronization packet based on the N-bit length, the second quotient value, and the third time counting value.

    Network device
    2.
    发明授权

    公开(公告)号:US11664967B2

    公开(公告)日:2023-05-30

    申请号:US17444909

    申请日:2021-08-11

    CPC classification number: H04L7/0033 H04J3/0667 H04J3/0697 H04L7/0091

    Abstract: A network device adapted for sending a synchronization packet to a slave device. The synchronization packet includes a timestamp field and a correction field. The network device includes a counting circuit, a communication chip, and a processor. The counting circuit is configured to provide a calendar time TOD. The communication chip includes a first port, a second port, and a timestamp circuit which has a bit number N. The processor is coupled to the first port of the communication chip. The processor is configured to: obtain a remainder R according to the calendar time TOD and the bit number N; and write the calendar time TOD and the remainder R into the synchronization packet.

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