公开(公告)号：US09195627B2

公开(公告)日：2015-11-24

申请号：US13946048

申请日：2013-07-19

Applicant: ACCTON TECHNOLOGY CORPORATION

Inventor： Chi-Hsu Chen ,  Yi-Liang Yeh ,  Yu-Yun Lee ,  Yuan-Hsiung Sung ,  Kuo-Jui Yu

IPC: G06F1/04 ,  G06F13/42

CPC classification number: G06F1/04 ,  G06F1/08 ,  G06F13/4291

Abstract: An apparatus and a method of controlling clock signals for a master device and a slave device are disclosed. The controlling apparatus includes: a first connection port coupled to a first clock line of the master device; a second connection port coupled to a second clock line of the slave device; and a control module receiving a first clock signal from the master device via the first connection port, producing a second clock signal according to the first clock signal, and transmitting the second clock signal to the slave device via the second connection port; wherein when the first clock signal is switched from a first logic level to a second logic level, the control module controls the first connection port to maintain the second logic level in a time interval.

Abstract translation: 公开了一种用于控制主设备和从设备的时钟信号的设备和方法。 控制装置包括：耦合到主设备的第一时钟线的第一连接端口; 耦合到所述从设备的第二时钟线的第二连接端口; 以及控制模块，经由所述第一连接端口从所述主设备接收第一时钟信号，根据所述第一时钟信号产生第二时钟信号，并经由所述第二连接端口将所述第二时钟信号发送到所述从设备; 其中当所述第一时钟信号从第一逻辑电平切换到第二逻辑电平时，所述控制模块控制所述第一连接端口以在时间间隔内维持所述第二逻辑电平。