Interconnection device
    1.
    发明授权
    Interconnection device 有权
    互连设备

    公开(公告)号:US08264948B2

    公开(公告)日:2012-09-11

    申请号:US12196984

    申请日:2008-08-22

    CPC classification number: H04L1/0045 G06F11/10 H04L1/0072 H04L2001/0097

    Abstract: A plurality of system board modules are connected to a crossbar module. An error detection unit detects an error in a packet received from a corresponding system board module. When an error is detected by the error detection unit, a transmission control unit issues a completion data generation request. When receiving the completion data generation request, a packet completion unit generates completion data. When receiving an error packet, a selector circuit outputs a completion packet in which completion data is provided in place of a data unit involving error.

    Abstract translation: 多个系统板模块连接到交叉开关模块。 错误检测单元检测从对应的系统板模块接收到的分组中的错误。 当错误检测单元检测到错误时,发送控制单元发出完成数据生成请求。 当接收到完成数据生成请求时,分组完成单元生成完成数据。 当接收到错误包时,选择器电路输出提供完成数据的完成包来代替涉及错误的数据单元。

    Parallel computer of a distributed storage type
    3.
    发明授权
    Parallel computer of a distributed storage type 失效
    分布式存储类型的并行计算机

    公开(公告)号:US5765202A

    公开(公告)日:1998-06-09

    申请号:US700835

    申请日:1996-08-21

    CPC classification number: G06F15/17 G06F15/8007

    Abstract: A parallel computer of a distributed storage type, which can omit an overhead time of a processing apparatus required for an address computation, is provided with an array address converting apparatus for generating a PE number of a PE retaining an array element that is an object of an access and an address on storage apparatus of the array element within the PE in each PE. Upon an access to an array element of array data, the processing apparatus activates the array address converting apparatus, a communicating apparatus gives an address on storage apparatus generated by the array address converting apparatus to a PE having a PE number generated by the array address converting apparatus to transmit access demand information for the array element. This parallel computer of a distributed storage type is applicable to a computer system for processing enormous data at a high speed such as numerical calculation, image processing or the like.

    Abstract translation: 可以省略分配存储类型的并行计算机,其可以省略地址计算所需的处理装置的开销时间,该阵列地址转换装置用于生成保留作为对象的数组元素的PE的PE号 每个PE内的PE内阵列元件的存储装置的访问和地址。 在访问阵列数据的阵列元素时,处理装置激活阵列地址转换装置,通信装置将由阵列地址转换装置产生的存储装置的地址赋予具有由阵列地址转换产生的PE号码的PE 传送数组元素的访问需求信息的装置。 这种分布式存储类型的并行计算机可应用于用于以诸如数值计算,图像处理等之类的高速处理大量数据的计算机系统。

    Data pre-fetch control device
    6.
    发明授权
    Data pre-fetch control device 失效
    数据预取控制装置

    公开(公告)号:US5412786A

    公开(公告)日:1995-05-02

    申请号:US158318

    申请日:1993-11-29

    Inventor: Yoshihiro Kusano

    CPC classification number: G06F9/3802 G06F12/0862 G06F9/383 G06F9/3832

    Abstract: A data processing device having a CPU and a memory device includes a unit for temporarily storing information concerning a predicted access which is expected to occur subsequent to the occurrence of an access. The unit is searched to obtain a predicted access address, which is activated in advance, so that data can be efficiently pre-fetched.

    Abstract translation: 具有CPU和存储装置的数据处理装置包括用于临时存储关于预期在访问发生之后发生的预测访问的信息的单元。 搜索该单元以获得预先激活的预测访问地址,使得可以有效地预取数据。

    ERROR CONTROL APPARATUS
    7.
    发明申请
    ERROR CONTROL APPARATUS 有权
    错误控制装置

    公开(公告)号:US20080310297A1

    公开(公告)日:2008-12-18

    申请号:US12196984

    申请日:2008-08-22

    CPC classification number: H04L1/0045 G06F11/10 H04L1/0072 H04L2001/0097

    Abstract: A plurality of system board modules are connected to a crossbar module. An error detection unit detects an error in a packet received from a corresponding system board module. When an error is detected by the error detection unit, a transmission control unit issues a completion data generation request. When receiving the completion data generation request, a packet completion unit generates completion data. When receiving an error packet, a selector circuit outputs a completion packet in which completion data is provided in place of a data unit involving error.

    Abstract translation: 多个系统板模块连接到交叉开关模块。 错误检测单元检测从对应的系统板模块接收到的分组中的错误。 当错误检测单元检测到错误时,发送控制单元发出完成数据生成请求。 当接收到完成数据生成请求时,分组完成单元生成完成数据。 当接收到错误包时,选择器电路输出提供完成数据的完成包来代替涉及错误的数据单元。

    Dynamic address translation allowing quick update of the change bit
    9.
    发明授权
    Dynamic address translation allowing quick update of the change bit 失效
    动态地址转换允许快速更新更改位

    公开(公告)号:US5497469A

    公开(公告)日:1996-03-05

    申请号:US939721

    申请日:1992-09-02

    CPC classification number: G06F12/1027

    Abstract: A dynamic address translation processing apparatus in a data processing system having a main memory for storing an address conversion table, and a central processing unit for converting a virtual address to a real address by referring the address conversion table. The central processing unit includes a first register for holding the virtual address, a second register for holding a table entry of the address conversion table corresponding to the virtual address held in the first register and, having an update bit indicative that a page in memory has been written to a third register for holding the real address of the table entry held in the second register, a comparison circuit for comparing the virtual address held in the first register with the other virtual address to be converted to the real address, and an update unit for updating the update bit in the table entry held in the second register. When the virtual address coincides with the other virtual address in the comparison circuit, the table entry converted by the update unit is written into an address of the main memory held in the third register.

    Abstract translation: 具有用于存储地址转换表的主存储器的数据处理系统中的动态地址转换处理装置,以及通过参考地址转换表将虚拟地址转换为真实地址的中央处理单元。 中央处理单元包括用于保存虚拟地址的第一寄存器,用于保存对应于保存在第一寄存器中的虚拟地址的地址转换表的表项的第二寄存器,以及具有指示存储器中的页的更新位 被写入到第三寄存器中,用于保持保存在第二寄存器中的表条目的实际地址,比较电路,用于比较保存在第一寄存器中的虚拟地址与要转换为实际地址的另一虚拟地址;以及更新 用于更新保存在第二寄存器中的表条目中的更新位的单元。 当虚拟地址与比较电路中的另一个虚拟地址一致时,由更新单元转换的表项被写入保存在第三寄存器中的主存储器的地址。

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