公开(公告)号：US08327081B2

公开(公告)日：2012-12-04

申请号：US12199444

申请日：2008-08-27

Applicant: Gou Sugizaki

Inventor： Gou Sugizaki

IPC: G06F12/08

CPC classification number: G06F12/0831

Abstract: A processor module having a cache device and a system controller having a copy TAG2 of a tag of the cache device configure a system to which a protocol representing the states of a data block of the cache device by six states, that is, an invalid state I, a shared state S, an exclusive state E, a modified state M, a shared modified state O, and a writable modified state W can be applied. In order to implement the concept, information about a new state in a cache device of a requester is included in a reply packet from the cache device for transmitting the data block. After the completion of the snooping process of the TAG2 until the reception of the reply packet from the cache device for transmitting the data block and the determination of the next state, an object data block is locked in the TAG2.

Abstract translation: 具有高速缓存设备的处理器模块和具有高速缓存设备的标签的复制TAG2的系统控制器配置一个系统，通过六种状态将代表高速缓存设备的数据块的状态的协议表示为无效状态 I，共享状态S，排他状态E，修改状态M，共享修改状态O和可写修改状态W。 为了实现该概念，关于请求者的缓存装置中的新状态的信息被包括在用于发送数据块的高速缓存装置的应答分组中。 在完成了TAG2的窥探处理之后，直到接收到用于发送数据块的缓存装置的应答分组和下一个状态的确定，目标数据块被锁定在TAG2中。

公开(公告)号：US08264948B2

公开(公告)日：2012-09-11

申请号：US12196984

申请日：2008-08-22

Applicant: Hiroshi Murakami ,  Yoshihiro Kusano ,  Gou Sugizaki ,  Satoshi Nakagawa

Inventor： Hiroshi Murakami ,  Yoshihiro Kusano ,  Gou Sugizaki ,  Satoshi Nakagawa

IPC: G01R31/08

CPC classification number: H04L1/0045 ,  G06F11/10 ,  H04L1/0072 ,  H04L2001/0097

Abstract: A plurality of system board modules are connected to a crossbar module. An error detection unit detects an error in a packet received from a corresponding system board module. When an error is detected by the error detection unit, a transmission control unit issues a completion data generation request. When receiving the completion data generation request, a packet completion unit generates completion data. When receiving an error packet, a selector circuit outputs a completion packet in which completion data is provided in place of a data unit involving error.

Abstract translation: 多个系统板模块连接到交叉开关模块。 错误检测单元检测从对应的系统板模块接收到的分组中的错误。 当错误检测单元检测到错误时，发送控制单元发出完成数据生成请求。 当接收到完成数据生成请求时，分组完成单元生成完成数据。 当接收到错误包时，选择器电路输出提供完成数据的完成包来代替涉及错误的数据单元。

公开(公告)号：US07979644B2

公开(公告)日：2011-07-12

申请号：US12199469

申请日：2008-08-27

Applicant: Gou Sugizaki ,  Satoshi Nakagawa

Inventor： Gou Sugizaki ,  Satoshi Nakagawa

IPC: G06F12/00

CPC classification number: G06F12/0831

Abstract: A multiprocessor system comprises a plurality of system controllers, each of which performs a snoop processing regarding a cache device in its charge. The system controllers adjust the number of steps of a snoop pipeline for the snoop processing according to communication time with the other system controllers. The number-of-steps adjustment absorbs the difference of the communication time in the results of the snoop for each scale of the multiprocessor system. When a retrial is determined by an address conflict or the like in the snoop processing, each of the system controllers resubmits the access to be retried to the snoop pipeline after waiting until no other access which may cause an address conflict precedes. The resubmission timing prevents infinite repetition of the retrial of the snoop processing in the system controllers.

Abstract translation: 多处理器系统包括多个系统控制器，每个系统控制器对其中的高速缓存设备执行窥探处理。 系统控制器根据与其他系统控制器的通信时间调整窥探处理的监听管道的步数。 步数调整吸收了多处理器系统的每个比例的窥探结果中的通信时间的差异。 当通过侦听处理中的地址冲突等来确定重试时，系统控制器中的每个系统控制器在等待之后重新提交要重试的访问到监听管道，直到不能引起地址冲突的其他访问先于之前。 重新提交时间阻止系统控制器中的窥探处理的重试的无限重复。

公开(公告)号：US20080320237A1

公开(公告)日：2008-12-25

申请号：US12199469

申请日：2008-08-27

Applicant: Gou SUGIZAKI ,  Satoshi Nakagawa

Inventor： Gou SUGIZAKI ,  Satoshi Nakagawa

IPC: G06F12/08

CPC classification number: G06F12/0831

Abstract: A multiprocessor system comprises a plurality of system controllers, each of which performs a snoop processing regarding a cache device in its charge. The system controllers adjust the number of steps of a snoop pipeline for the snoop processing according to communication time with the other system controllers. The number-of-steps adjustment absorbs the difference of the communication time in the results of the snoop for each scale of the multiprocessor system. When a retrial is determined by an address conflict or the like in the snoop processing, each of the system controllers resubmits the access to be retried to the snoop pipeline after waiting until no other access which may cause an address conflict precedes. The resubmission timing prevents infinite repetition of the retrial of the snoop processing in the system controllers.

Abstract translation: 多处理器系统包括多个系统控制器，每个系统控制器对其中的高速缓存设备执行窥探处理。 系统控制器根据与其他系统控制器的通信时间调整窥探处理的监听管道的步数。 步数调整吸收了多处理器系统的每个比例的窥探结果中的通信时间的差异。 当通过侦听处理中的地址冲突等来确定重试时，系统控制器中的每个系统控制器在等待之后重新提交要重试的访问到监听管道，直到不能引起地址冲突的其他访问先于之前。 重新提交时间阻止系统控制器中的窥探处理的重试的无限重复。

公开(公告)号：US20080310297A1

公开(公告)日：2008-12-18

申请号：US12196984

申请日：2008-08-22

Applicant: Hiroshi MURAKAMI ,  Yoshihiro Kusano ,  Gou Sugizaki ,  Satoshi Nakagawa

Inventor： Hiroshi MURAKAMI ,  Yoshihiro Kusano ,  Gou Sugizaki ,  Satoshi Nakagawa

IPC: H04L1/24

CPC classification number: H04L1/0045 ,  G06F11/10 ,  H04L1/0072 ,  H04L2001/0097

Abstract: A plurality of system board modules are connected to a crossbar module. An error detection unit detects an error in a packet received from a corresponding system board module. When an error is detected by the error detection unit, a transmission control unit issues a completion data generation request. When receiving the completion data generation request, a packet completion unit generates completion data. When receiving an error packet, a selector circuit outputs a completion packet in which completion data is provided in place of a data unit involving error.

Abstract translation: 多个系统板模块连接到交叉开关模块。 错误检测单元检测从对应的系统板模块接收到的分组中的错误。 当错误检测单元检测到错误时，发送控制单元发出完成数据生成请求。 当接收到完成数据生成请求时，分组完成单元生成完成数据。 当接收到错误包时，选择器电路输出提供完成数据的完成包来代替涉及错误的数据单元。

公开(公告)号：US20080313411A1

公开(公告)日：2008-12-18

申请号：US12199444

申请日：2008-08-27

Applicant: Gou SUGIZAKI

Inventor： Gou SUGIZAKI

IPC: G06F12/08

CPC classification number: G06F12/0831

Abstract: A processor module having a cache device and a system controller having a copy TAG2 of a tag of the cache device configure a system to which a protocol representing the states of a data block of the cache device by six states, that is, an invalid state I, a shared state S, an exclusive state E, a modified state M, a shared modified state O, and a writable modified state W can be applied. In order to implement the concept, information about a new state in a cache device of a requester is included in a reply packet from the cache device for transmitting the data block. After the completion of the snooping process of the TAG2 until the reception of the reply packet from the cache device for transmitting the data block and the determination of the next state, an object data block is locked in the TAG2.

Abstract translation: 具有高速缓存设备的处理器模块和具有高速缓存设备的标签的复制TAG2的系统控制器配置一个系统，通过六种状态将代表高速缓存设备的数据块的状态的协议表示为无效状态 I，共享状态S，排他状态E，修改状态M，共享修改状态O和可写修改状态W。 为了实现该概念，关于请求者的缓存装置中的新状态的信息被包括在用于发送数据块的高速缓存装置的应答分组中。 在完成了TAG2的窥探处理之后，直到接收到用于发送数据块的缓存装置的应答分组和下一个状态的确定，目标数据块被锁定在TAG2中。