公开(公告)号：US20120218846A1

公开(公告)日：2012-08-30

申请号：US13463609

申请日：2012-05-03

申请人： Yong Gu KANG

发明人： Yong Gu KANG

IPC分类号： G11C29/00

CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5006

摘要： A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

摘要翻译： 半导体存储装置的测试电路包括：测试控制信号生成单元，被配置为在测试信号被使能之后启用有效信号，并且基本上将控制信号保持在使能状态直到预充电定时信号 已启用 以及预充电控制单元，其被配置为当初始位线预充电信号处于禁用状态时，将控制信号反转为输出反相信号作为位线预充电信号。

公开(公告)号：US08194482B2

公开(公告)日：2012-06-05

申请号：US12650727

申请日：2009-12-31

申请人： Yong Gu Kang

发明人： Yong Gu Kang

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5006

摘要： A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state.

摘要翻译： 半导体存储装置的测试电路包括：测试控制信号生成单元，被配置为在测试信号被使能之后启用有效信号，并且基本上将控制信号保持在使能状态直到预充电定时信号 已启用 以及预充电控制单元，其被配置为当初始位线预充电信号处于禁用状态时，将控制信号反转为输出反相信号作为位线预充电信号。

公开(公告)号：US20090091363A1

公开(公告)日：2009-04-09

申请号：US12170243

申请日：2008-07-09

申请人： Yong Gu Kang ,  Yong Mi Kim

发明人： Yong Gu Kang ,  Yong Mi Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/10 ,  H03K5/135 ,  H03L7/0814

摘要： A DLL circuit including a first clock signal dividing block configured to selectively divide a frequency of a reference clock signal according to whether a lock completion signal is enabled, a phase comparing block configured to generate a phase comparison signal by comparing phases of a clock signal transmitted from the first clock signal dividing block with a feedback clock signal, and an operation mode setting block configured to generate the lock completion signal in response to the phase comparison signal is described herein.

摘要翻译： 一种DLL电路，包括：第一时钟信号分配块，被配置为根据是否启用锁定完成信号来选择性地分频参考时钟信号的频率;相位比较块，被配置为通过比较发送的时钟信号的相位来产生相位比较信号 从具有反馈时钟信号的第一时钟信号分割块和被配置为响应于相位比较信号产生锁定完成信号的操作模式设置块被描述。

公开(公告)号：US08794473B2

公开(公告)日：2014-08-05

申请号：US13476537

申请日：2012-05-21

申请人： Yong Gu Kang

发明人： Yong Gu Kang

IPC分类号： B65D45/22 ,  B65D45/20 ,  B65D45/16

CPC分类号： B65D45/22 ,  B60R7/04 ,  B65D45/16 ,  B65D45/20

摘要： A console box includes a housing defining an article accommodating space therein and having an opening formed at a front side thereof; a cover coupled to the front side of the housing via hinge couplers disposed at opposite sides of the cover; dampers, each being disposed between each of the hinge couplers of the cover and the housing and controlling an opening speed of the cover; and a torsion spring disposed between each of the hinge couplers of the cover and the housing and elastically supporting the cover. The console box further includes a hinge cover disposed outside each of the hinge couplers of the cover and preventing the cover and the torsion spring from separating from each other.

摘要翻译： 控制箱包括壳体，其在其中限定物品容纳空间，并且具有形成在其前侧的开口; 通过布置在所述盖的相对侧上的铰链联接器联接到所述壳体的前侧的盖; 阻尼器，每个都布置在盖和壳体的每个铰链联接器之间并且控制盖的打开速度; 以及扭簧，其设置在所述盖和所述壳体的每个铰链联接器之间并且弹性地支撑所述盖。 控制台还包括铰链盖，其设置在盖的每个铰链联接器的外侧，并防止盖和扭簧相互分离。

公开(公告)号：US08398130B2

公开(公告)日：2013-03-19

申请号：US12325961

申请日：2008-12-01

申请人： Jin Wan Park ,  Yong Gu Kang ,  Chang Min Lee ,  Jong Sun Lee

发明人： Jin Wan Park ,  Yong Gu Kang ,  Chang Min Lee ,  Jong Sun Lee

IPC分类号： E05B63/20

CPC分类号： B60R7/06 ,  B60R21/045 ,  E05B77/06 ,  E05B83/28 ,  E05C19/022 ,  Y10T292/0863 ,  Y10T292/304 ,  Y10T292/546

摘要： An anti-opening apparatus locks a tray so as to prevent the tray from opening when impact such as head impact is applied to a crash pad. In the tray anti-opening apparatus, the tray is mounted so as to be pulled into or out of a housing fixedly coupled to a crash pad. A rotary bar is hinged to the housing at an intermediate portion thereof, extends toward the tray on one side thereof, extends in a direction which crosses the extension direction of one side thereof on the other side thereof, and is rotated such that one side thereof approaches one surface of the tray when impact is applied to the crash pad. A pin is coupled on one side of the rotary bar, and a free end of the pin is inserted into an insertion hole formed in the tray when the rotary bar is rotated.

摘要翻译： 防打开装置锁定托盘，以防止当冲击（例如头部撞击）施加到碰撞垫时托盘打开。 在托盘打开装置中，托盘被安装成被拉入固定地联接到碰撞垫的壳体中。 旋转杆在其中间部分处铰接到壳体，在其一侧向托盘延伸，在与其一侧的延伸方向相交的方向上延伸，并在其一侧旋转，使得其一侧 当撞击施加到碰撞垫时，接近托盘的一个表面。 销连接在旋转杆的一侧，当旋转杆旋转时，销的自由端插入形成在托盘中的插入孔中。

公开(公告)号：US20120026821A1

公开(公告)日：2012-02-02

申请号：US12914164

申请日：2010-10-28

申请人： Yong-Gu KANG

发明人： Yong-Gu KANG

IPC分类号： G11C7/00 ,  G11C8/12

CPC分类号： G11C11/406 ,  G11C11/40611 ,  G11C11/40618

摘要： A semiconductor device includes a plurality of bank groups including at least two banks, respectively, and a plurality of address counters corresponding to the plurality of bank groups in a one-to-one manner. A refresh operation of a selected bank group is performed in response to a bank group refresh command.

摘要翻译： 半导体器件分别包括至少两个存储体的多个存储体组和与该多个存储体组一一对应的多个地址计数器。 响应于组组刷新命令执行所选择的组组的刷新操作。

公开(公告)号：US20110075498A1

公开(公告)日：2011-03-31

申请号：US12650491

申请日：2009-12-30

申请人： Choung Ki Song ,  Young Do Hur ,  Sang Sic Yoon ,  Yong Gu Kang ,  Gyung Tae Kim

发明人： Choung Ki Song ,  Young Do Hur ,  Sang Sic Yoon ,  Yong Gu Kang ,  Gyung Tae Kim

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/12 ,  G11C11/401 ,  G11C2029/1204

摘要： A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense amplifier driving control unit configured to generate a first voltage supply control signal, a second voltage supply control signal and a third voltage supply control signal in response to the test signal, a sense amplifier enable test signal, a first voltage supply signal, a second voltage supply signal and a third voltage supply signal; and a voltage supply unit configured to provide the core voltage, an external voltage and a ground voltage to a sense amplifier with an open bit line structure in response to the first to third voltage supply control signals.

摘要翻译： 半导体存储装置包括：预充电电压控制单元，被配置为响应于测试信号选择性地输出位线预充电电压或核心电压作为控制电压; 位线均衡单元，被配置为将位线预充电到所述控制电压; 感测放大器驱动控制单元，被配置为响应于测试信号产生第一电压供应控制信号，第二电压供应控制信号和第三电压供应控制信号，感测放大器使能测试信号，第一电压供应信号， 第二电压供给信号和第三电压供给信号; 以及电压供给单元，被配置为响应于所述第一至第三电压供给控制信号，将具有开放位线结构的所述核心电压，外部电压和接地电压提供给具有开放位线结构的读出放大器。

公开(公告)号：US07499359B2

公开(公告)日：2009-03-03

申请号：US11354125

申请日：2006-02-15

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

IPC分类号： G11C7/00

CPC分类号： G01K7/01

摘要： A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

摘要翻译： 可以驱动温度传感器的温度传感器指令信号发生器和包括该温度传感器的半导体存储器件。 温度传感器指令信号发生器可以使用主时钟（CLK）信号，时钟使能（CKE）信号，行地址选择（RAS）信号， 列地址选择（CAS）信号，写使能（WE）信号和芯片选择（CS）信号，其中所述指令信号可以对应于自刷新模式，自动刷新模式和 长tRAS模式。 半导体存储器件可以包括温度传感器和温度传感器指令信号发生器。

公开(公告)号：US07298189B2

公开(公告)日：2007-11-20

申请号：US10965985

申请日：2004-10-15

申请人： Yong Gu Kang ,  Jun Hyun Chun

发明人： Yong Gu Kang ,  Jun Hyun Chun

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： The DLL circuit detects a frequency of an external clock signal and adjusts a coarse delay during a DLL circuit operation, thereby quickly terminating a feedback operation of the DLL circuit and having a reduced circuit area of a delay line. Therefore, the DLL circuit can be used for next generation high-integration and high-frequency memory devices such as DDR2 SDRAMs.

摘要翻译： DLL电路检测外部时钟信号的频率，并且在DLL电路操作期间调整粗略的延迟，从而快速地终止DLL电路的反馈操作并且具有减小的延迟线的电路面积。 因此，DLL电路可用于下一代高集成度和高​​频存储器件，如DDR2 SDRAM。

公开(公告)号：US20060195289A1

公开(公告)日：2006-08-31

申请号：US11354125

申请日：2006-02-15

申请人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

发明人： Jong-Hyun Choi ,  Dong-Il Seo ,  Yong-Gu Kang ,  Jung-Yong Choi ,  Young-Hun Seo

IPC分类号： G01K1/00

CPC分类号： G01K7/01

摘要： A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.