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    Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus
    3.
    发明授权
    Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus 有权
    包含中断处理装置的等模型处理器和处理器的中断处理装置和方法

    公开(公告)号：US08516231B2

    公开(公告)日：2013-08-20

    申请号：US12695266

    申请日：2010-01-28

    Applicant: Il-hyun Park ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Yeon-gon Cho ,  Bernhard Egger

    Inventor： Il-hyun Park ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Yeon-gon Cho ,  Bernhard Egger

    IPC: G06F15/00 ,  G06F9/00 ,  G06F9/44

    CPC classification number: G06F9/3836 ,  G06F9/327

    Abstract: An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support determining apparatus determines whether an instruction input to a processor decoder is a multiple latency instruction, compares a current latency of the instruction with a remaining latency if the instruction is a multiple latency instruction, and updates the current latency to the remaining latency if the current latency is greater than the remaining latency.

    Abstract translation: 提供了一种用于等模型处理器的中断支持确定装置和方法，以及包括中断支持确定装置的处理器。 中断支持确定装置确定输入到处理器解码器的指令是否是多等待时间指令，如果指令是多等待时间指令，则将指令的当前等待时间与剩余延迟进行比较，并将当前等待时间更新为剩余延迟，如果 当前的延迟大于剩余的延迟。

    HARDWARE DEBUGGING APPARATUS AND METHOD FOR SOFTWARE PIPELINED PROGRAM
    4.
    发明申请
    HARDWARE DEBUGGING APPARATUS AND METHOD FOR SOFTWARE PIPELINED PROGRAM 有权
    用于软件管道程序的硬件调试装置和方法

    公开(公告)号：US20130191620A1

    公开(公告)日：2013-07-25

    申请号：US13734526

    申请日：2013-01-04

    Applicant: Hee-Jun SHIM ,  Yeon-Gon CHO

    Inventor： Hee-Jun SHIM ,  Yeon-Gon CHO

    IPC: G06F9/38

    CPC classification number: G06F9/38 ,  G06F11/3636 ,  G06F11/3648

    Abstract: Provided is a hardware debugging apparatus and method for a software-pipelined program. The hardware debugging apparatus and method overcome a currency problem caused during hardware debugging in the software-pipelined program by guarding certain execution blocks and restarting the processing of the software-pipelined program.

    Abstract translation: 提供了一种用于软件流水线程序的硬件调试装置和方法。 硬件调试装置和方法通过保护某些执行块并重新启动软件流水线程序的处理，克服了软件流水线程序硬件调试过程中造成的货币问题。

    RECONFIGURABLE PROCESSOR AND OPERATING METHOD OF THE SAME
    6.
    发明申请
    RECONFIGURABLE PROCESSOR AND OPERATING METHOD OF THE SAME 有权
    可重构加工器及其操作方法

    公开(公告)号：US20100174885A1

    公开(公告)日：2010-07-08

    申请号：US12563350

    申请日：2009-09-21

    Applicant: Il-hyun PARK ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Yeon-gon Cho ,  Bernhard Egger ,  Woon Seo

    Inventor： Il-hyun PARK ,  Soo-jung Ryu ,  Dong-hoon Yoo ,  Yeon-gon Cho ,  Bernhard Egger ,  Woon Seo

    IPC: G06F15/76 ,  G06F9/00

    CPC classification number: G06F15/7867 ,  G06F9/30072 ,  Y02D10/12 ,  Y02D10/13

    Abstract: Provided are a reconfigurable processor and operating method thereof. The reconfigurable processor may use a configuration memory distributed to each operation unit. The distributed configuration memory may be separated into a distributed operation configuration memory including configuration information about an operation of a function unit, and a distributed routing configuration memory including configuration information about routing. The distributed operation configuration memory may be activated according to a predicate signal.

    Abstract translation: 提供了一种可重构处理器及其操作方法。 可重构处理器可以使用分配给每个操作单元的配置存储器。 分布式配置存储器可以被分成包括关于功能单元的操作的配置信息的分布式操作配置存储器，以及包括关于路由的配置信息的分布式路由配置存储器。 可以根据谓词信号激活分布式操作配置存储器。

    Computing apparatus and method of handling interrupt
    9.
    发明授权
    Computing apparatus and method of handling interrupt 有权
    处理中断的计算设备和方法

    公开(公告)号：US08495345B2

    公开(公告)日：2013-07-23

    申请号：US12639663

    申请日：2009-12-16

    Applicant: Dong-hoon Yoo ,  Soo-jung Ryu ,  Yeon-gon Cho ,  Bernhard Egger ,  Il-hyun Park

    Inventor： Dong-hoon Yoo ,  Soo-jung Ryu ,  Yeon-gon Cho ,  Bernhard Egger ,  Il-hyun Park

    IPC: G06F15/80

    CPC classification number: G06F9/3879 ,  G06F9/4812

    Abstract: A computing apparatus and method of handling an interrupt are provided. The computing apparatus includes a coarse-grained array, a host processor, and an interrupt supervisor. When an interrupt occurs in the coarse-grained array while performing a loop operation, the host processor processes the interrupt, and the interrupt supervisor may perform mode switching between the coarse-grained array and the host processor.

    Abstract translation: 提供了一种处理中断的计算装置和方法。 计算装置包括粗粒子阵列，主处理器和中断主管。 当执行循环操作时，在粗粒度阵列中发生中断时，主机处理器处理中断，中断主管可以在粗粒度阵列与主机处理器之间执行模式切换。

    PIPELINE PROCESSOR AND AN EQUAL MODEL CONSERVATION METHOD
    10.
    发明申请
    PIPELINE PROCESSOR AND AN EQUAL MODEL CONSERVATION METHOD 有权
    管道加工器和等效模型保存方法

    公开(公告)号：US20110296143A1

    公开(公告)日：2011-12-01

    申请号：US12982201

    申请日：2010-12-30

    Applicant: Heejun Shim ,  Yenjo Han ,  Jae-Young Kim ,  Yeon-Gon Cho ,  Jinseok Lee

    Inventor： Heejun Shim ,  Yenjo Han ,  Jae-Young Kim ,  Yeon-Gon Cho ,  Jinseok Lee

    IPC: G06F9/38

    CPC classification number: G06F11/1407 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867

    Abstract: A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.

    Abstract translation: 提供了一种满足相等模型的等待时间限制的流水线处理器。 流水线处理器包括处理多级指令的流水线处理单元和相等模型补偿器，以存储位于流水线处理单元中的部分或全部指令的处理结果，并写入处理结果 基于每个指令的延迟，在一个寄存器文件中。

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