公开(公告)号：US20130001795A1

公开(公告)日：2013-01-03

申请号：US13407295

申请日：2012-02-28

Applicant: Teck Guan LIM ,  Ying Ying Lim ,  Yee Mong Khoo ,  Navas Khan Oratti Kalandar ,  Faxing Che ,  Ser Choong Chong ,  Soon Wee David Ho ,  Shan Gao ,  Rui Li

Inventor： Teck Guan LIM ,  Ying Ying Lim ,  Yee Mong Khoo ,  Navas Khan Oratti Kalandar ,  Faxing Che ,  Ser Choong Chong ,  Soon Wee David Ho ,  Shan Gao ,  Rui Li

IPC: H01L23/48

CPC classification number: H01L24/96 ,  H01L23/3107 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/96 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00

Abstract: A wafer level package is provided. The wafer level package includes at least one chip with at least one electronic component, and at least one connecting chip with at least one through-silicon via, wherein the at least one through-silicon via is electrically coupled to the at least one chip. Further embodiments relate to a method of forming the wafer level package.

Abstract translation: 提供晶圆级封装。 晶片级封装包括具有至少一个电子部件的至少一个芯片和至少一个具有至少一个穿硅通孔的连接芯片，其中所述至少一个穿硅通孔电耦合到所述至少一个芯片。 另外的实施例涉及形成晶片级封装的方法。

公开(公告)号：US20120126419A1

公开(公告)日：2012-05-24

申请号：US13055525

申请日：2008-07-24

Applicant: Vaidyanathan Kripesh ,  Navas Khan Orattikalandar ,  Srinivasa Rao Vempati ,  Yak Long Samuel Lim ,  Yee Mong Khoo ,  Chee Houe Khong ,  Xiao Wu Zhang ,  Tai Chong Chai ,  Hon-Shing John Lau

Inventor： Vaidyanathan Kripesh ,  Navas Khan Orattikalandar ,  Srinivasa Rao Vempati ,  Yak Long Samuel Lim ,  Yee Mong Khoo ,  Chee Houe Khong ,  Xiao Wu Zhang ,  Tai Chong Chai ,  Hon-Shing John Lau

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L29/0657 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/161 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/1624 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3025 ,  H01L2924/35 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: According to one embodiment of the present invention, a substrate arrangement is provided. The substrate arrangement includes a first substrate; a second substrate positioned above the first substrate, the second substrate comprising a first through hole; a third substrate positioned above the second substrate, the third substrate comprising a second through hole; a first electrically conductive interconnect pillar positioned on the first substrate and extending from the first substrate through the first through hole to electrically contact the third substrate; and a second electrically conductive interconnect pillar positioned on the second substrate and extending from the second substrate through the second through hole. A method of manufacturing a substrate arrangement is also provided.

Abstract translation: 根据本发明的一个实施例，提供了一种衬底布置。 衬底布置包括第一衬底; 位于所述第一基板上方的第二基板，所述第二基板包括第一通孔; 位于所述第二基板上方的第三基板，所述第三基板包括第二通孔; 位于所述第一基板上并且从所述第一基板延伸穿过所述第一通孔的第一导电互连柱，以与所述第三基板电接触; 以及第二导电互连柱，其定位在所述第二基板上并且从所述第二基板延伸穿过所述第二通孔。 还提供了一种制造衬底布置的方法。