公开(公告)号：US20120169402A1

公开(公告)日：2012-07-05

申请号：US13417548

申请日：2012-03-12

Applicant: TOSHIAKI KAWASAKI ,  YASUHIRO AGATA ,  MASANORI SHIRAHAMA ,  TOSHIHIRO KOUGAMI ,  KATSUYA ARAI

Inventor： TOSHIAKI KAWASAKI ,  YASUHIRO AGATA ,  MASANORI SHIRAHAMA ,  TOSHIHIRO KOUGAMI ,  KATSUYA ARAI

IPC: H01H37/76

CPC classification number: H01L27/0207 ,  G11C17/18 ,  H01L23/5256 ,  H01L27/0288 ,  H01L27/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an electric fuse circuit and a program protective circuit. The electric fuse circuit includes a fuse element and a transistor connected together in series and placed between a program power supply and a grounding, and controlling sections. The program protective circuit is placed in parallel with the electric fuse circuit and between the program power supply and the grounding. When a surge voltage is applied between the program power supply and the grounding, the foregoing structure allows a part of a surge electric current can flow through the program protective circuit.

Abstract translation: 半导体器件包括电熔丝电路和程序保护电路。 电熔丝电路包括串联连接在一起的一个熔丝元件和一个晶体管，并放置在一个程序电源和一个接地之间，以及控制部分。 程序保护电路与电熔丝电路并联在程序电源和接地之间。 当在程序电源和接地之间施加浪涌电压时，上述结构允许一部分浪涌电流可以流过程序保护电路。

公开(公告)号：US08094498B2

公开(公告)日：2012-01-10

申请号：US12792295

申请日：2010-06-02

Applicant: Yasue Yamamoto ,  Masanori Shirahama ,  Yasuhiro Agata ,  Toshiaki Kawasaki

Inventor： Yasue Yamamoto ,  Masanori Shirahama ,  Yasuhiro Agata ,  Toshiaki Kawasaki

IPC: G11C16/04

CPC classification number: G11C16/0441 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

Abstract: In a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, and a decode device including a second MOS transistor and a third MOS transistor, are arranged in array. This attains nonvolatile memory capable of bit by bit selective erase arranged in array to thus reduce the core area remarkably.

Abstract translation: 在通过在浮动栅极中积累电荷来存储数据的非易失性半导体存储器件中，每个包括作为读取器件的第一MOS晶体管的存储器单元，由作为电容耦合器件的第一电容器构成的位单元和第二电容器 擦除装置，以及包括第二MOS晶体管和第三MOS晶体管的解码装置。 这实现了能够排列成阵列的逐位选择性擦除的非易失性存储器，从而显着地减小了核心区域。

公开(公告)号：US20110007595A1

公开(公告)日：2011-01-13

申请号：US12888158

申请日：2010-09-22

Applicant: Yasuhiro AGATA ,  Yutaka Terada ,  Kenji Misumi ,  Masanori Shirahama ,  Mitsuaki Hayashi

Inventor： Yasuhiro AGATA ,  Yutaka Terada ,  Kenji Misumi ,  Masanori Shirahama ,  Mitsuaki Hayashi

IPC: G11C17/16

CPC classification number: G11C11/4072 ,  G11C17/165 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/4402 ,  G11C2029/5002

Abstract: An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.

Abstract translation: 电子设备系统包括：半导体集成电路，具有存储有关半导体集成电路的特性的信息的非易失性存储器; 以及控制器，被配置为控制半导体集成电路。 控制器具有基于存储在非易失性存储器中的信息调整对半导体集成电路的访问参数的功能。

公开(公告)号：US07623380B2

公开(公告)日：2009-11-24

申请号：US11526057

申请日：2006-09-25

Applicant: Yasue Yamamoto ,  Yasuhiro Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki

Inventor： Yasue Yamamoto ,  Yasuhiro Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki

IPC: G11C16/04

CPC classification number: G11C16/0416 ,  G11C2216/10 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11558

Abstract: A nonvolatile semiconductor memory device for storing data by accumulating charge in a floating gate includes a plurality of MOS transistors sharing the floating gate. In the device, a PMOS is used for coupling during writing and an n-type depletion MOS (DMOS) is used for coupling during erasure. Coupling of channel inversion capacitance by the PMOS is used for writing and coupling of depletion capacitance by the n-type DMOS is used for erasure, thereby increasing the erase speed without increase of area, as compared to a conventional three-transistor nonvolatile memory element.

Abstract translation: 用于通过在浮动栅极中累积电荷来存储数据的非易失性半导体存储器件包括共享浮置栅极的多个MOS晶体管。 在器件中，在写入期间使用PMOS耦合并且在擦除期间使用n型耗尽MOS（DMOS）耦合。 与传统的三晶体管非易失性存储元件相比，通过PMOS将沟道反转电容耦合用于n型DMOS的耗尽电容的写入和耦合用于擦除，从而增加擦除速度而不增加面积。

公开(公告)号：US07535748B2

公开(公告)日：2009-05-19

申请号：US11905532

申请日：2007-10-02

Applicant: Masanori Shirahama ,  Yasuhiro Agata ,  Yasue Yamamoto

Inventor： Masanori Shirahama ,  Yasuhiro Agata ,  Yasue Yamamoto

IPC: G11C11/00

CPC classification number: G11C11/16 ,  G11C7/12 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0028 ,  G11C2213/72

Abstract: A memory cell is constructed by connecting in series a variable-resistance element having a resistance which is varied by application of a positive voltage to one terminal (first node) thereof using a potential at the other terminal thereof as a reference and a diode which allows a current to flow therethrough by application of a positive voltage to the other terminal thereof using a potential at one terminal (second node) thereof as a reference. The first node is connected to the corresponding column select line and the second node is connected to the corresponding row select line. Then, to a non-selected row select line, a potential higher than when the row select line is selected is applied by using a row control circuit. By using column-select-line driver circuits, predetermined potentials corresponding to a non-selection period, a data write period, a reset period, and a data read period are applied to the column select line.

Abstract translation: 存储单元通过串联连接可变电阻元件，该可变电阻元件具有通过使用其另一端子处的电位作为参考而将正电压施加到其一个端子（第一节点）而变化的电阻，以及允许 使用在其一个端子（第二节点）处的电位作为参考，通过向其另一端施加正电压而流过其中的电流。 第一个节点连接到相应的列选择线，第二个节点连接到相应的行选择行。 然后，对于未选择的行选择线，通过使用行控制电路来应用比选择行选择线高的电位。 通过使用列选择线驱动电路，将对应于非选择周期，数据写入周期，复位周期和数据读取周期的预定电位施加到列选择线。

公开(公告)号：US20080036527A1

公开(公告)日：2008-02-14

申请号：US11882974

申请日：2007-08-08

Applicant: Ryuji Nishihara ,  Yasuhiro Agata ,  Toshiaki Kawasaki ,  Shinichi Sumi

Inventor： Ryuji Nishihara ,  Yasuhiro Agata ,  Toshiaki Kawasaki ,  Shinichi Sumi

IPC: H01H37/76

CPC classification number: G11C17/18 ,  G11C17/16

Abstract: The invention provides an electrical fuse device comprising: a plurality of fuse cores, each having an electrical fuse element and a switching element serially connected to the electrical fuse element; a program control circuit generating a program shift signal by sequentially shifting a program control transmission signal in synchronization with an effective program clock signal and subsequently generating a program signal to be sent to each of the switching elements in the plurality of fuse cores based on program data and the program shift signal; and a program clock control circuit controlling the conducting and non-conducting states of a program clock signal in accordance with a program clock enable signal and, when the program clock signal is in a conducting state, transmitting the program clock signal to the program control circuit as the effective program clock signal.

Abstract translation: 本发明提供一种电熔丝装置，包括：多个熔丝芯，每个熔丝芯具有电熔丝元件和串联连接到电熔丝元件的开关元件; 程序控制电路，通过与有效的程序时钟信号同步地依次移位程序控制传输信号并随后根据程序数据产生要发送到多个保险丝核心中的每一个开关元件的程序信号来产生程序移位信号 和程序移位信号; 以及程序时钟控制电路，其根据程序时钟使能信号控制编程时钟信号的导通状态和非导通状态，并且当所述程序时钟信号处于导通状态时，将所述程序时钟信号发送到所述程序控制电路 作为有效的程序时钟信号。

公开(公告)号：US07254079B2

公开(公告)日：2007-08-07

申请号：US11324243

申请日：2006-01-04

Applicant: Shinichi Sumi ,  Yasuhiro Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki ,  Ryuji Nishihara

Inventor： Shinichi Sumi ,  Yasuhiro Agata ,  Masanori Shirahama ,  Toshiaki Kawasaki ,  Ryuji Nishihara

IPC: G11C17/18 ,  G11C7/00

CPC classification number: G11C17/18

Abstract: An electrical fuse circuit of the present invention includes a plurality of electrical fuse cores (1) each of which has an electrical fuse element (3) and a switch transistor (4) connected in series with each other, and shift registers (2) connected to the plurality of electrical fuse cores (1) to program the electrical fuse elements (3). Program enable signals (Si) are sequentially generated and transferred by the shift registers (2), the switch transistors (4) are sequentially brought into conduct according to the program enable signals (Si) and the information of program data (Di), and the electrical fuse elements (3) are blown one by one.

Abstract translation: 本发明的电熔丝电路包括多个电熔丝芯（1），每个电熔丝芯具有彼此串联连接的电熔丝元件（3）和开关晶体管（4），并且移位寄存器（2）连接 到多个电熔丝芯（1）以编程电熔丝元件（3）。 程序使能信号（Si）由移位寄存器（2）依次产生和传送，开关晶体管（4）根据程序使能信号（Si）和程序数据（Di）的信息依次导通， 电熔丝元件（3）被一个接一个地吹出。

公开(公告)号：US20120146156A1

公开(公告)日：2012-06-14

申请号：US13396892

申请日：2012-02-15

Applicant: MASANORI SHIRAHAMA ,  YASUHIRO AGATA ,  TOSHIAKI KAWASAKI ,  YUICHI HIROFUJI ,  TAKAYUKI YAMADA

Inventor： MASANORI SHIRAHAMA ,  YASUHIRO AGATA ,  TOSHIAKI KAWASAKI ,  YUICHI HIROFUJI ,  TAKAYUKI YAMADA

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629

Abstract: A semiconductor device includes an MIS transistor and an electric fuse. The MIS transistor includes a gate insulating film formed on the semiconductor substrate, and a gate electrode including a first polysilicon layer, a first silicide layer, and a first metal containing layer made of a metal or a conductive metallic compound. The electric fuse includes an insulating film formed on the semiconductor substrate, a second polysilicon layer formed over the insulating film, and a second silicide layer formed on the second polysilicon layer.

Abstract translation: 半导体器件包括MIS晶体管和电熔丝。 MIS晶体管包括形成在半导体衬底上的栅极绝缘膜和包括第一多晶硅层，第一硅化物层和由金属或导电金属化合物制成的第一金属含有层的栅电极。 电熔丝包括形成在半导体衬底上的绝缘膜，形成在绝缘膜上的第二多晶硅层和形成在第二多晶硅层上的第二硅化物层。

公开(公告)号：US08125820B2

公开(公告)日：2012-02-28

申请号：US12880608

申请日：2010-09-13

Applicant: Akira Masuo ,  Yasuhiro Agata

Inventor： Akira Masuo ,  Yasuhiro Agata

IPC: G11C11/00

CPC classification number: G11C11/419 ,  G11C7/12

Abstract: A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or source of each first transistor is connected to an input of the corresponding first logic gate, and the gate of each first transistor is connected to an output of the corresponding first logic gate. The first transistors are driven by pulses.

Abstract translation: 提供了应用位线电位降压技术的存储器。 存储器包括IO块，其包括控制相对于存储器单元的列提供的第一位线的电位的第一晶体管，以及控制第一晶体管的第一逻辑门。 每个第一晶体管的漏极或源极连接到对应的第一逻辑门的输入，并且每个第一晶体管的栅极连接到相应的第一逻辑门的输出端。 第一晶体管由脉冲驱动。

公开(公告)号：US20110205827A1

公开(公告)日：2011-08-25

申请号：US12672265

申请日：2009-09-11

Applicant: Yasuhiro Agata ,  Noriaki Narumi ,  Yoshinobu Yamagami ,  Akira Masuo

Inventor： Yasuhiro Agata ,  Noriaki Narumi ,  Yoshinobu Yamagami ,  Akira Masuo

IPC: G11C5/14

CPC classification number: G11C11/413 ,  G11C5/147 ,  H01L23/5286 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A system LSI (100) having a logic circuit (104) and a plurality of SRAM macros (103) includes a power supply circuit (102) configured to receive a voltage (VDDP) supplied from the outside of the system LSI (100), and to generate a stabilized voltage (VDDM) lower than the voltage (VDDP). An SRAM memory cell (103a) of each of the plurality of SRAM macros (103) is supplied with the voltage (VDDM) generated by the power supply circuit (102), and an SRAM logic circuit (103b) of each of the plurality of SRAM macros (103) is supplied with a voltage (VDD) supplied from the outside. In addition, the logic circuit (104) is supplied with the voltage (VDD) from the outside.

Abstract translation: 具有逻辑电路（104）和多个SRAM宏（103）的系统LSI（100）包括：电源电路（102），被配置为接收从系统LSI（100）的外部提供的电压（VDDP） 并产生低于电压（VDDP）的稳定电压（VDDM）。 多个SRAM宏（103）中的每一个的SRAM存储单元（103a）被提供有由电源电路（102）产生的电压（VDDM）和多个SRAM宏中的每一个的SRAM逻辑电路（103b） SRAM宏（103）提供从外部提供的电压（VDD）。 此外，逻辑电路（104）从外部提供电压（VDD）。