公开(公告)号：US20170084335A1

公开(公告)日：2017-03-23

申请号：US15263724

申请日：2016-09-13

Applicant: Wook-Ghee HAHN ,  Chang-Yeon YU

Inventor： Wook-Ghee HAHN ,  Chang-Yeon YU

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C16/0483 ,  G11C16/20 ,  G11C16/24

Abstract: A row decoder of the semiconductor memory device includes a decoding and precharging unit that is connected between a high voltage node and a block word line, wherein the decoding and precharging unit precharges the block word line, and wherein the decoding and precharging unit includes one or more decoding transistors that decode an address and form a transmission path for transmitting a block selection voltage. The row decoder further includes a pass transistor block that transmits one or more row driving voltages to row lines in response to the block selection voltage, wherein the block selection voltage is boosted according to a switching operation of the pass transistor block.

公开(公告)号：US20070183245A1

公开(公告)日：2007-08-09

申请号：US11642105

申请日：2006-12-20

Applicant: Hee-Won Lee ,  Dae-Seok Byeon ,  Wook-Ghee Hahn

Inventor： Hee-Won Lee ,  Dae-Seok Byeon ,  Wook-Ghee Hahn

IPC: G11C17/18

CPC classification number: G11C16/30 ,  G11C5/147 ,  G11C16/04 ,  G11C17/18 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: Control circuits for a voltage regulator of a semiconductor memory device include an option fuse circuit and a fusing control circuit. The option fuse circuit includes a plurality of fuses and a selection circuit that selects one of the plurality of fuses responsive to a control signal. An output voltage associated with the voltage reset circuit is adjusted responsive to a state of the selected one of the plurality of fuses. A fusing control circuit generates the control signal to allow multiple adjustments of the output voltage by the voltage reset circuit. The option fuse circuit may be a plurality of option fuse circuits and the output voltage may be adjusted responsive to the states of the respective selected ones of the plurality of fuses of the option fuse circuits.

Abstract translation: 用于半导体存储器件的电压调节器的控制电路包括选件熔丝电路和定影控制电路。 选项熔丝电路包括多个保险丝和选择电路，其根据控制信号选择多个保险丝之一。 响应于所选择的多个保险丝的状态来调整与电​​压复位电路相关联的输出电压。 熔断控制电路产生控制信号以允许电压复位电路对输出电压进行多次调节。 选项保险丝电路可以是多个选项保险丝电路，并且可以响应于选项保险丝电路的多个保险丝中的相应选择的保险丝的状态来调整输出电压。

公开(公告)号：US20070182398A1

公开(公告)日：2007-08-09

申请号：US11698945

申请日：2007-01-29

Applicant: Wook-Ghee Hahn

Inventor： Wook-Ghee Hahn

IPC: G05F1/00

CPC classification number: G05F1/56

Abstract: Provided is a voltage regulator. The voltage regulator includes a level down shifter reducing an applied high voltage, a voltage divider dividing the reduced high voltage to generate a first division result, a comparator comparing a reference voltage to the first division result, and a driver generating an output voltage based on the comparison result and providing the output voltage to the voltage divider. The voltage divider divides the output voltage to generate a second division result serving as a voltage control signal fed back to the level down shifter.

Abstract translation: 提供电压调节器。 电压调节器包括降低施加的高电压的电平降低移位器，分压降低的高电压以产生第一分割结果的分压器，将参考电压与第一分频结果进行比较的比较器，以及产生基于 比较结果，并提供输出电压分压器。 分压器分压输出电压以产生用作反馈到电平降低变换器的电压控制信号的第二分频结果。

公开(公告)号：US20060061411A1

公开(公告)日：2006-03-23

申请号：US11025765

申请日：2004-12-28

Applicant: Wook-Ghee Hahn ,  Dae-Seok Byeon

Inventor： Wook-Ghee Hahn ,  Dae-Seok Byeon

IPC: G05F1/10

CPC classification number: H02M3/07 ,  H02M1/14

Abstract: The present invention disclosed herein is a high voltage generator circuit. The high voltage generator circuit includes a charge pump and a pump clock signal generator. The pump clock signal is gated to the charge pump when the high voltage is below a target voltage. After the high voltage reaches the target voltage, the high voltage cyclically falls below the target voltage. After the high voltage reaches the target voltage, a pump clock generator block circuit limits the transmission of the pump clock signal so that only N clock signals are gate to the charge pump each cycle, where N is the number one or greater.

Abstract translation: 本文公开的本发明是高压发生器电路。 高压发生器电路包括电荷泵和泵时钟信号发生器。 当高电压低于目标电压时，泵时钟信号被选通到电荷泵。 高电压达到目标电压后，高压周期性下降到目标电压以下。 在高电压达到目标电压之后，泵时钟发生器电路限制泵时钟信号的传输，从而每个周期只有N个时钟信号被选通到电荷泵，其中N是一个或更多个。

公开(公告)号：US20060044923A1

公开(公告)日：2006-03-02

申请号：US11020517

申请日：2004-12-22

Applicant: Wook-Ghee Hahn ,  Sung-Soo Lee ,  Dae-Seok Byeon

Inventor： Wook-Ghee Hahn ,  Sung-Soo Lee ,  Dae-Seok Byeon

IPC: G11C8/00

CPC classification number: G11C8/08 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5641

Abstract: A non-volatile memory device includes non-volatile memory cells, a respective one of which is configured to store a single bit in a single bit mode, and to store more than one bit in a multi-bit mode. A single voltage divider is configured to generate at a least a first program voltage for the non-volatile memory cells in the single bit mode, and to generate at least a second program voltage that is different from the first program voltage, for the non-volatile memory cells in the multi-bit mode.

Abstract translation: 非易失性存储器件包括非易失性存储器单元，其相应​​的一个被配置为以单位模式存储单个位，并且以多位模式存储多个位。 单个分压器被配置为以单比特模式在非易失性存储器单元中产生至少第一编程电压，并且生成与第一编程电压不同的至少第二编程电压， 多位模式下的易失性存储单元。

公开(公告)号：US20130250691A1

公开(公告)日：2013-09-26

申请号：US13892427

申请日：2013-05-13

Applicant: Moo Sung Kim ,  Wook Ghee Hahn

Inventor： Moo Sung Kim ,  Wook Ghee Hahn

IPC: G11C16/10

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10

Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

公开(公告)号：US20120120727A1

公开(公告)日：2012-05-17

申请号：US13289282

申请日：2011-11-04

Applicant: Moo Sung Kim ,  Wook Ghee Hahn

Inventor： Moo Sung Kim ,  Wook Ghee Hahn

IPC: G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10

Abstract: A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage.

Abstract translation: 一种在存储器件中提供工作电压的方法包括：将一个读取电压施加到所选择的字线上，同时对与所选择的字线相邻的字线中的至少一个未选择的字线施加第一通过电压; 并且在剩余的未选择字线（除了施加了第一通过电压的至少一个未选择的字线之外）施加第二通过电压的同时。 第一通过电压的电平高于第二通过电压的电平。 可以基于读取电压的电平来设置第一通过电压的电平。

公开(公告)号：US20100046292A1

公开(公告)日：2010-02-25

申请号：US12458999

申请日：2009-07-29

Applicant: Wook-ghee Hahn ,  Jai-ick Son ,  Youn-yeol Lee

Inventor： Wook-ghee Hahn ,  Jai-ick Son ,  Youn-yeol Lee

IPC: G11C16/06 ,  G11C29/00 ,  G11C8/00 ,  G11C8/10

CPC classification number: G11C29/76 ,  G11C16/0483 ,  G11C2029/4402

Abstract: A non-volatile memory device and a bad block remapping method use some of main blocks as remapping blocks to replace a bad block in a main cell block and selects remapping blocks using existing block address signals. Thus, separate bussing of remapping block address signals is not needed. The bad block remapping includes comparing an external block address input from an external source to a stored bad block address, generating a bad block flag signal when the external block address is identical to the stored bad block address, generating a remapping block address selecting the remapping blocks in response to a remapping address corresponding to the bad block address, selecting one of the external block address and the remapping block address in response to the bad block flag signal to create a selected address, and outputting a row address signal in accordance with the selected address.

Abstract translation: 非易失性存储器件和坏块重映射方法使用一些主块作为重新映射块来替换主单元块中的坏块并且使用现有块地址信号来选择重映射块。 因此，不需要单独的重映射块地址信号的总线。 坏块重映射包括将外部源的外部块地址输入与存储的坏块地址进行比较，当外部块地址与存储的坏块地址相同时产生坏块标志信号，生成选择重映射的重映射块地址 响应于与坏块地址对应的重映射地址，响应于坏块标志信号选择外部块地址和重映射块地址中的一个以创建所选择的地址，并且根据该块地址信号输出行地址信号 选定的地址。

公开(公告)号：US20090257278A1

公开(公告)日：2009-10-15

申请号：US12247325

申请日：2008-10-08

Applicant: Wook-ghee HAHN

Inventor： Wook-ghee HAHN

IPC: G11C16/04 ,  G11C8/08 ,  G11C16/06

CPC classification number: G11C16/08 ,  G11C8/10 ,  G11C16/0483

Abstract: A flash memory device includes at least two mats and a row decoder shared by the mats. Each mat includes multiple word lines, bit lines, and blocks that share the bit lines. The row decoder includes a block decoder that generates a block selection signal for selecting a block, a block word line boosting circuit that generates a high voltage block word line signal in response to the block selection signal, a word line driver that drives word line drive signals driving the word lines of the selected block using drive voltages according to an operation mode and the word lines of an unselected block using a first bias voltage, and a string selection line driver that drives a string selection signal of the selected block using a drive voltage according to the operation mode and the string selection signal of the unselected block using a second bias voltage.

Abstract translation: 闪速存储器件包括由垫共享的至少两个垫和行解码器。 每个垫包括共享位线的多个字线，位线和块。 行解码器包括块解码器，其生成用于选择块的块选择信号，响应于块选择信号产生高电压块字线信号的块字线升压电路，驱动字线驱动的字线驱动器 根据操作模式和使用第一偏置电压的未选择块的字线的驱动电压来驱动所选块的字线的信号;以及串选择线驱动器，其使用驱动器驱动所选块的串选择信号 根据操作模式的电压和使用第二偏置电压的未选择块的串选择信号。

公开(公告)号：US07821832B2

公开(公告)日：2010-10-26

申请号：US12247325

申请日：2008-10-08

Applicant: Wook-ghee Hahn

Inventor： Wook-ghee Hahn

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C8/10 ,  G11C16/0483

Abstract: A flash memory device includes at least two mats and a row decoder shared by the mats. Each mat includes multiple word lines, bit lines, and blocks that share the bit lines. The row decoder includes a block decoder that generates a block selection signal for selecting a block, a block word line boosting circuit that generates a high voltage block word line signal in response to the block selection signal, a word line driver that drives word line drive signals driving the word lines of the selected block using drive voltages according to an operation mode and the word lines of an unselected block using a first bias voltage, and a string selection line driver that drives a string selection signal of the selected block using a drive voltage according to the operation mode and the string selection signal of the unselected block using a second bias voltage.

Abstract translation: 闪速存储器件包括由垫共享的至少两个垫和行解码器。 每个垫包括共享位线的多个字线，位线和块。 行解码器包括块解码器，其生成用于选择块的块选择信号，响应于块选择信号产生高电压块字线信号的块字线升压电路，驱动字线驱动的字线驱动器 根据操作模式和使用第一偏置电压的未选择块的字线的驱动电压来驱动所选块的字线的信号;以及串选择线驱动器，其使用驱动器驱动所选块的串选择信号 根据操作模式的电压和使用第二偏置电压的未选择块的串选择信号。