公开(公告)号：US5627377A

公开(公告)日：1997-05-06

申请号：US525998

申请日：1995-09-07

Applicant: William J. Hamilton, Jr. ,  David R. Rhiger

Inventor： William J. Hamilton, Jr. ,  David R. Rhiger

IPC: G01T1/24 ,  H01L25/04 ,  H01L27/14 ,  H01L27/146 ,  H01L31/00 ,  H01L31/0352 ,  H01L31/09

CPC classification number: G01T1/241 ,  H01L25/043 ,  H01L27/146 ,  H01L31/0352 ,  H01L2924/0002

Abstract: A three terminal solid-state ionizing radiation detector (10) includes a first layer (18) of a substantially intrinsic Group II-VI compound semiconductor material, such as CdZnTe. The first layer is responsive to incident ionizing radiation for generating electron-hole pairs. The detector further includes a second layer (24) of Group II-VI compound semiconductor material and a third layer (20) of Group II-VI compound semiconductor material that is interposed between first surfaces of the first layer and the second layer. The third layer functions as a grid layer. A first electrical contact (12, 17) is coupled to a second surface of the first layer, a second electrical contact (29, 30) is coupled to a second surface of the second layer, and a third electrical contact (22) is coupled to the third layer for connecting the detector to an external circuit that establishes an electric field across the detector. The electric field causes holes to drift away from the grid layer towards the first contact while electrons drift towards and through the grid layer, through the second layer, and towards the second contact for generating a detectable output signal pulse. Because of the presence of the grid layer only the electrons contribute to the output pulse. The grid layer has a conductivity type such that electrons are a minority charge carrier within the grid layer.

Abstract translation: 三端固态电离辐射检测器（10）包括基本上本征的II-VI族化合物半导体材料（例如CdZnTe）的第一层（18）。 第一层响应入射电离辐射以产生电子 - 空穴对。 检测器还包括第II-VI族化合物半导体材料的第二层（24）和介于第一层和第二层的第一表面之间的第II-VI族化合物半导体材料的第三层（20）。 第三层用作网格层。 第一电触点（12,17）耦合到第一层的第二表面，第二电触点（29,30）耦合到第二层的第二表面，并且第三电触点（22）被耦合 到第三层，用于将检测器连接到在检测器上建立电场的外部电路。 电场使得空穴从网格层朝向第一接触漂移，同时电子朝向并穿过网格层，穿过第二层，朝着第二接触移动以产生可检测的输出信号脉冲。 由于栅格层的存在，只有电子有助于输出脉冲。 栅格层具有导电类型，使得电子是网格层内的少数电荷载体。

公开(公告)号：US5616925A

公开(公告)日：1997-04-01

申请号：US486497

申请日：1995-06-07

Applicant: David R. Rhiger ,  Sanghamitra Sen ,  William J. Hamilton, Jr.

Inventor： David R. Rhiger ,  Sanghamitra Sen ,  William J. Hamilton, Jr.

IPC: G01T1/24 ,  H01L31/115 ,  H01L31/18 ,  H01L31/0256

CPC classification number: G01T1/24 ,  H01L31/115 ,  H01L31/1832

Abstract: Gamma ray detectors (20, 130) are provided with a detector layer (30) that is formed of Hg.sub.x Cd.sub.1-x-y Zn.sub.y Te, wherein 0

Abstract translation: γ射线检测器（20,130）设置有由Hg x C 1d-x-y ZnyTe形成的检测器层（30），其中0

公开(公告)号：US06455931B1

公开(公告)日：2002-09-24

申请号：US09859618

申请日：2001-05-15

Applicant: William J. Hamilton, Jr. ,  Michael Ray ,  Eli E. Gordon ,  Christopher L. Fletcher ,  Ronald W. Berry

Inventor： William J. Hamilton, Jr. ,  Michael Ray ,  Eli E. Gordon ,  Christopher L. Fletcher ,  Ronald W. Berry

IPC: H01L2334

CPC classification number: H01L27/14683 ,  H01L27/14601 ,  H01L27/14643 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A monolithic microelectronic array structure includes a microelectronic integrated circuit array having a first plurality of microelectronic integrated circuit elements each deposited on a front side of a substrate. The substrates are physically discontinuous so that each substrate comprises a substrate island which is physically separated from the other substrate islands. The monolithic microelectronic array structure optionally includes a first plurality of input/output elements with a respective input/output element associated with and directly connected to each of the microelectronic integrated circuit elements, and a second plurality of electrically conductive interconnects extending between the microelectronic integrated circuit elements of adjacent substrate islands. The monolithic microelectronic array structure may be planar, or it may be curved.

Abstract translation: 单片微电子阵列结构包括微电子集成电路阵列，其具有分别沉积在衬底的前侧上的第一多个微电子集成电路元件。 衬底物理不连续，使得每个衬底包括与其它衬底岛物理分离的衬底岛。 单片微电子阵列结构可选地包括具有与每个微电子集成电路元件相关联并直接连接到每个微电子集成电路元件的相应输入/输出元件的第一多个输入/输出元件，以及在微电子集成电路之间延伸的第二多个导电互连 相邻衬底岛的元素。 单片微电子阵列结构可以是平面的，或者它可以是弯曲的。

公开(公告)号：US06627865B1

公开(公告)日：2003-09-30

申请号：US09859619

申请日：2001-05-15

Applicant: William J. Hamilton, Jr. ,  Paul R. Norton ,  Eli E. Gordon ,  Ronald W. Berry

Inventor： William J. Hamilton, Jr. ,  Paul R. Norton ,  Eli E. Gordon ,  Ronald W. Berry

IPC: H01L2700

CPC classification number: H01L27/1446

Abstract: An integrated optical device array structure has a plurality of interconnected solid state microelectronic optical device elements associated together on a substrate structure. The optical device elements may be optical detectors or optical emitters. Each optical device element lies on a nonplanar optical array surface. Each optical device element includes an opto-electronic device that interconverts an optical signal and an opto-electronic device electrical signal, and an electrical interface circuit that is in electrical communication with the opto-electronic device electrical signal. The optical device array structure may be fabricated by preparing a flat array of optical device elements and deforming the flat array into the required shape.

Abstract translation: 集成的光学器件阵列结构具有在衬底结构上连接在一起的多个互连的固态微电子光学器件元件。 光学器件元件可以是光学检测器或光发射器。 每个光学器件元件位于非平面光学阵列表面上。 每个光学器件元件包括互相转换光信号和光电器件电信号的光电器件，以及与光电器件电信号电通信的电接口电路。 光学器件阵列结构可以通过制备光学器件元件的平坦阵列并将平坦阵列变形成所需形状来制造。

公开(公告)号：US5723866A

公开(公告)日：1998-03-03

申请号：US670478

申请日：1996-06-26

Applicant: William J. Hamilton, Jr.

Inventor： William J. Hamilton, Jr.

IPC: H01L27/146 ,  H01L27/144 ,  H01L31/09

CPC classification number: H01L27/1465

Abstract: A large area radiation detector (1) includes a volume of semiconductor material (24) that is responsive to ionizing radiation for generating charge carriers, a first electrode (26) coupled to one surface of the volume of semiconductor material, and a plurality of second electrodes (20, 22) coupled to a second surface of the volume of semiconductor material. Individual ones of the second electrodes are associated with an underlying region of the volume of semiconductor material for collecting charge carriers from the underlying region. The detector further includes circuitry (30, 31, 32) coupled to the plurality of second electrodes for summing charge carriers collected by the plurality of second electrodes to produce an output signal, and a mechanism for selectively decoupling individual ones of the second electrodes from the circuitry. In one embodiment the circuitry includes electrically conductive traces (16) that couple individual ones of the second electrodes to a summing junction (31), and the mechanism for selectively decoupling includes physically opening a trace to disconnect the second electrode from the summing junction. In a further embodiment the mechanism for selectively decoupling includes a semiconductor switch (34) that is coupled in series with each of the traces.

Abstract translation: 大面积辐射检测器（1）包括响应于用于产生电荷载流子的电离辐射的半导体材料体积（24），耦合到半导体材料体积的一个表面的第一电极（26）和多个第二 耦合到半导体材料体积的第二表面的电极（20,22）。 第二电极中的单个电极与用于从下面的区域收集电荷载流子的半导体材料的体积的下面的区域相关联。 检测器还包括耦合到多个第二电极的电路（30,31,32），用于对由多个第二电极收集的电荷载体求和以产生输出信号，以及用于选择性地将第二电极中的单个电极与 电路。 在一个实施例中，电路包括将第二电极中的单个电极耦合到求和结（31）的导电迹线（16），并且用于选择性去耦的机构包括物理地打开迹线以将第二电极与加法连接断开。 在另一实施例中，用于选择性去耦的机构包括与每个迹线串联耦合的半导体开关（34）。

公开(公告)号：US5449927A

公开(公告)日：1995-09-12

申请号：US245147

申请日：1994-05-16

Applicant: William J. Hamilton, Jr. ,  Scott M. Johnson ,  William L. Ahlgren

Inventor： William J. Hamilton, Jr. ,  Scott M. Johnson ,  William L. Ahlgren

IPC: H01L21/20 ,  H01L21/205 ,  H01L21/36 ,  H01L29/225 ,  H01L29/267 ,  H01L31/0264 ,  H01L29/161

CPC classification number: H01L21/02562 ,  H01L21/02381 ,  H01L21/02477 ,  H01L21/0248 ,  H01L21/02502 ,  H01L21/0251 ,  H01L29/225 ,  H01L29/267

Abstract: A layer (32) of a HgCdTe compound epitaxially contacts a buffer structure, which in turn epitaxially contacts a silicon substrate (22). The buffer structure is formed of II-VI compounds, and preferably includes at least one layer (24) of a ZnSeTe compound epitaxially contacting the silicon substrate (22) and a layer (30) of a CdZnTe compound overlying the ZnSeTe compound layer (24). The ZnSeTe compound layer (24) may be provided as a single graded layer having a composition of ZnSe adjacent to the silicon and a composition of ZnTe remote from the silicon, or as two distinct sublayers with a ZnSe sublayer (26) adjacent to the silicon substrate (22) and a ZnTe sublayer (28) remote from the silicon substrate (22).

Abstract translation: HgCdTe化合物的层（32）外延地接触缓冲结构，缓冲结构又外延地接触硅衬底（22）。 缓冲结构由II-VI化合物形成，并且优选包括外延接触硅衬底（22）的ZnSeTe化合物的至少一层（24）和覆盖ZnSeTe化合物层（24）的CdZnTe化合物的层（30） ）。 ZnSeTe化合物层（24）可以被提供为具有与硅相邻的ZnSe的组成的单个梯度层和远离硅的ZnTe组成，或者作为与邻近硅的ZnSe子层（26）的两个不同的子层 衬底（22）和远离硅衬底（22）的ZnTe子层（28）。

公开(公告)号：US06828545B1

公开(公告)日：2004-12-07

申请号：US09859575

申请日：2001-05-15

Applicant: William J. Hamilton, Jr. ,  Eli E. Gordon ,  Ronald W. Berry

Inventor： William J. Hamilton, Jr. ,  Eli E. Gordon ,  Ronald W. Berry

IPC: H01L3100

CPC classification number: H01L27/1465 ,  H01L2924/351

Abstract: A hybrid microelectronic array structure is fabricated from a readout integrated circuit array of microelectronic integrated circuits and a supported array of supported islands. The supported islands include one or more supported elements, with a respective supported element for each of the readout integrated circuits. The supported array is made by depositing the first semiconductor region onto a supported substrate and depositing the second semiconductor region onto the first semiconductor region, and defining supported islands as electrically isolated segments. On each supported element, a first interconnect is formed to the first semiconductor region and a second interconnect is formed to the second semiconductor region. The supported array is joined to the readout integrated circuit array by an interconnect structure, preferably a bump interconnect structure, to form the hybrid microelectronic array structure, with each readout integrated electrically interconnected to the respective one of the supported elements.

Abstract translation: 混合微电子阵列结构由微电子集成电路的读出集成电路阵列和支持的岛的支持阵列制成。 支撑的岛包括一个或多个受支撑的元件，以及用于每个读出集成电路的相应的支撑元件。 支撑的阵列通过将第一半导体区域沉积到受支撑的衬底上并将第二半导体区域沉积到第一半导体区域上并且将支撑的岛作为电隔离段来制造。 在每个支撑元件上，第一互连形成于第一半导体区域，第二互连形成于第二半导体区域。 支撑的阵列通过互连结构（优选地是凸块互连结构）连接到读出集成电路阵列，以形成混合微电子阵列结构，其中每个读出器电互连到相应的一个支持元件。