Abstract:
FIG. 1 is a front perspective view of a bar cart showing my new design; FIG. 2 is a left side view thereof; FIG. 3 is a right side view thereof; FIG. 4 is a front view thereof; FIG. 5 is a rear view thereof; FIG. 6 is a top plan view thereof; and, FIG. 7 is a bottom plan view thereof. Broken lines in the drawings depict portions of the bar cart that form no part of the claimed design.
Abstract:
An apparatus and method for a two-stage linear/nonlinear interference cancellation comprising processing a receive signal to produce a first descrambled signal; and processing the first descrambled signal to produce a detected signal. In one aspect, a first interference canceller module is used for processing the received signal and a second interference canceller module is used for processing the first descrambled signal. In one aspect, the first interference canceller is a linear interference canceller (IC) and the second interference canceller is a linear/nonlinear interference canceller (IC).
Abstract:
This invention discloses semiconductor power device that includes a plurality of top electrical terminals disposed near a top surface of a semiconductor substrate. Each and every one of the top electrical terminals comprises a terminal contact layer formed as a silicide contact layer near the top surface of the semiconductor substrate. The trench gates of the semiconductor power device are opened from the top surface of the semiconductor substrate and each and every one of the trench gates comprises the silicide layer configured as a recessed silicide contact layer disposed on top of every on of the trench gates slightly below a top surface of the semiconductor substrate surround the trench gate.
Abstract:
A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
Abstract:
A semiconductor device embodiment includes a substrate, an active gate trench in the substrate, and an asymmetric trench in the substrate. The asymmetric trench has a first trench wall and a second trench wall, the first trench wall is lined with oxide having a first thickness, and the second trench wall is lined with oxide having a second thickness that is different from the first thickness. Another semiconductor device embodiment includes a substrate, an active gate trench in the substrate; and a source polysilicon pickup trench in the substrate. The source polysilicon pickup trench includes a polysilicon electrode, and top surface of the polysilicon electrode is below a bottom of a body region. Another semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.
Abstract:
A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
Abstract:
A method for fabricating a semiconductor device includes forming a plurality of trenches, including applying a first mask, forming a first polysilicon region in at least some of the plurality of trenches, forming a inter-polysilicon dielectric region and a termination protection region, including applying a second mask, forming a second polysilicon region in the at least some of the plurality of trenches, forming a first electrical contact to the first polysilicon region and forming a second electrical contact to the second polysilicon region, including applying a third mask, disposing a metal layer, and forming a source metal region and a gate metal region, including applying a fourth mask.
Abstract:
Systems and methods for symbol detection using sub-constellations are provided. In one aspect of the disclosure, an apparatus is provided. The apparatus comprises a processing unit configured to process received chips into received symbols for a plurality of users, a first detection unit configured to detect first components of user symbols for the plurality of users based on the received symbols and a computation unit configured to compute a portion of the received symbols due to the first components of the user symbols. The apparatus further comprises a second detection unit configured to detect second components of the user symbols based on the received symbols with the computed portion removed and a combining unit configured to detect the user symbols by combining the first components of the user symbols with the respective second components of the user symbols.
Abstract:
Systems and methods for inter-cell interference cancellation are provided. In one aspect of the disclosure, an apparatus is provided. The apparatus comprises a cell computation unit configured to compute receive chips for a first interfering cell and a subtraction unit configured to remove the computed receive chips for the first interfering cell from received chips at a receiver. The apparatus further comprises a processing unit configured to process the received chips with the computed receive chips for the first interfering cell removed into received symbols and a detection unit configured to detect user symbols for a target cell from the received symbols.
Abstract:
A compact air pump and valve package includes pump and valve assemblies integral with a pressure housing defining inlet ports and a plurality of fittings for connecting air lines to an interior of the pressure housing. The linear diaphragm pump assembly has a permanent magnetic shuttle mounting two diaphragms reciprocated by an electromagnet. The valve assembly has a plurality of solenoid valves disposed within the pressure housing, each solenoid valve being operable to control flow into or out of the pressure housing through an associated one of the plurality of fittings. Thus, no tubes or hoses are required to transfer air from the pump assembly to the valves. The housing has special mounts to isolate vibration arising from movement of the shuttle.