公开(公告)号：US20100147799A1

公开(公告)日：2010-06-17

申请号：US12711344

申请日：2010-02-24

Applicant: Dong-Keun Kim ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

Inventor： Dong-Keun Kim ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC: C23F1/00

CPC classification number: H01L21/76819 ,  C09G1/02 ,  H01L21/31053

Abstract: In an embodiment, a chemical mechanical polishing method for a substrate having a first layer and a stepped portion. A surface of the first layer is positioned above an upper face of the stepped portion. A polishing process for selectively removing the stepped portion is performed on the first layer by using a first slurry composition that has a self-stopping characteristic so that the first layer is changed into a second layer having a substantially flat surface. A second polishing process is performed using a second slurry composition that does not have the self-stopping characteristic, until the upper face of the stepped portion is exposed.

Abstract translation: 在一个实施方案中，一种用于具有第一层和阶梯部分的基材的化学机械抛光方法。 第一层的表面位于台阶部的上表面的上方。 通过使用具有自停特性的第一浆料组合物在第一层上进行用于选择性去除台阶部分的抛光工艺，使得第一层变成具有基本平坦表面的第二层。 使用不具有自停特性的第二浆料组合物进行第二抛光处理，直到阶梯部分的上表面露出。

公开(公告)号：US07709319B2

公开(公告)日：2010-05-04

申请号：US11450269

申请日：2006-06-12

Applicant: Yeol Jon ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

Inventor： Yeol Jon ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC: H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10852

Abstract: Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.

Abstract translation: 提供一种包括在基板表面上方延伸的垂直取向的电容器的半导体器件以及制造这样的器件的方法，其中在半导体衬底上限定了单元和外围区域之间的单元，外围和边界区域。 电容器形成在电池区域中，在外围区域设置模具图案，并且在边界区域中设置细长的虚拟图案。 虚拟图案包括边界开口，其中在形成下电极期间在细长的内侧壁上和在基板的暴露部分上形成薄层。 然后形成具有基本上相同高度的模具图案和下部电极结构，使得随后的绝缘中间层呈现大致平坦的表面，即在电池区域和外围区域之间没有显着的步进差异。

公开(公告)号：US20100096681A1

公开(公告)日：2010-04-22

申请号：US12654255

申请日：2009-12-15

Applicant: Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

Inventor： Kyoung-Yun Baek ,  Yong-Sun Ko ,  Hak Kim ,  Yong-Kug Bae

IPC: H01L27/108

CPC classification number: H01L27/0207 ,  H01L27/10888

Abstract: In a 6F2 cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

Abstract translation: 在存储器件的6F2单元结构及其制造方法中，多个有源区可以在两端部具有第一区域，在中心部分可以具有第二区域。 位线接触焊盘的一部分可以位于第二区域上，另一部分可以位于基板的不与多个有源区域重叠的第三区域上。 位线可以与第三区域的位线接触焊盘连接。 尽管6F2结构的单元电池，电池结构也可以更容易地形成。 多个有源区域可以具有包括主轴和短轴的椭圆形状。 多个有源区域可以被定位在长轴方向上，从而形成有源行，并且可以以这样的结构定位在短轴方向上，使得多个有源区域的中心与相邻的活动区域的中心 相邻活动行中的区域。

公开(公告)号：US07579284B2

公开(公告)日：2009-08-25

申请号：US11482773

申请日：2006-07-10

Applicant: Byoung-Moon Yoon ,  Ji-Hong Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim

Inventor： Byoung-Moon Yoon ,  Ji-Hong Kim ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC: H01L21/311

CPC classification number: C09K13/04 ,  H01L21/32134

Abstract: Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present invention relate to an etching solution having an etching selectivity between a polysilicon layer and an oxide layer, a method of forming a pattern using an etching solution using the same, a method of manufacturing a multiple gate oxide layer using the same, and a method of manufacturing a flash memory device using the same. An etching solution including hydrogen peroxide (H2O2) and ammonium hydroxide (NH4OH) by a volume ratio of about 1:2 to about 1:10 mixed in water. In a method of forming a pattern and methods of manufacturing a multiple gate oxide layer and a flash memory device, a polysilicon layer may be formed on a substrate. An insulation layer pattern including an opening exposing the polysilicon layer may be formed on the polysilicon layer. The polysilicon layer exposed by the insulation layer pattern may be etched using the etching solution. A polysilicon layer pattern may be formed on the substrate using the etching solution.

Abstract translation: 本发明的示例性实施例涉及一种蚀刻溶液，使用该方法形成图案的方法，使用该蚀刻溶液的多栅极氧化物层的制造方法以及使用其制造闪存器件的方法。 本发明的其它示例性实施例涉及在多晶硅层和氧化物层之间具有蚀刻选择性的蚀刻溶液，使用其使用蚀刻溶液形成图案的方法，使用该栅极氧化物层的方法 以及使用其制造闪存器件的方法。 包含在水中混合的体积比为约1:2至约1:10的过氧化氢（H 2 O 2）和氢氧化铵（NH 4 OH）的蚀刻溶液。 在形成图案的方法和制造多栅极氧化物层和闪存器件的方法中，可以在衬底上形成多晶硅层。 可以在多晶硅层上形成包括露出多晶硅层的开口的绝缘层图案。 可以使用蚀刻溶液蚀刻由绝缘层图案暴露的多晶硅层。 可以使用蚀刻溶液在衬底上形成多晶硅层图案。

公开(公告)号：US20090090899A1

公开(公告)日：2009-04-09

申请号：US12285531

申请日：2008-10-08

Applicant: Young-Soo Lim ,  Yong-Sun Ko ,  Sung-Un Kwon ,  Jae-Seung Hwang

Inventor： Young-Soo Lim ,  Yong-Sun Ko ,  Sung-Un Kwon ,  Jae-Seung Hwang

IPC: H01L45/00

CPC classification number: H01L45/12 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.

Abstract translation: 一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成 在顶部电极的上表面上以及顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层 绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

公开(公告)号：US07498253B2

公开(公告)日：2009-03-03

申请号：US11679722

申请日：2007-02-27

Applicant: Sung-Un Kwon ,  Yong-Sun Ko

Inventor： Sung-Un Kwon ,  Yong-Sun Ko

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76895

Abstract: A local interconnection wiring structure method for forming the same reduces the likelihood of a short between a local interconnection layer of gate electrodes and an active region by forming a common aperture so as to have a determined aperture between the local interconnection layer and the active region on an insulation film of a semiconductor substrate. Methods of forming the local interconnection wire can include forming a first etching mask pattern that has a size longer than a length between inner ends of adjacent gate electrodes formed on a semiconductor substrate and covered with an insulation film. The etching mask simultaneously has a length the same as or shorter than the length between outer ends of the gate electrodes. The insulation film exposed in the first etching mask pattern is subsequently etched so that the insulation film remains higher than a highest height of the gate electrodes, so as to form a recess pattern. The first etching mask pattern is then removed and a second etching mask pattern is formed so as to partially expose the insulation film provided within the recess pattern. The insulation film within the recess pattern is etched to form apertures for exposing a partial surface of the gate electrodes. The second etching mask pattern is then removed. The recess pattern and the apertures are then filled with conductive material to form a local interconnection layer for connecting between the gate electrodes.

Abstract translation: 用于形成其的局部互连配线结构方法通过形成公共孔径来减小栅电极的局部互连层与有源区之间的短路的可能性，以便在局部互连层和有源区之间具有确定的孔径 半导体衬底的绝缘膜。 形成局部互连线的方法可以包括形成第一蚀刻掩模图案，其具有比形成在半导体衬底上并被绝缘膜覆盖的相邻栅电极的内端之间的长度的长度。 蚀刻掩模同时具有与栅电极的外端之间的长度相同或更短的长度。 随后蚀刻在第一蚀刻掩模图案中暴露的绝缘膜，使得绝缘膜保持高于栅电极的最高高度，以形成凹陷图案。 然后去除第一蚀刻掩模图案，并且形成第二蚀刻掩模图案，以便部分地暴露设置在凹槽图案内的绝缘膜。 蚀刻凹槽图形内的绝缘膜以形成用于暴露栅电极的局部表面的孔。 然后去除第二蚀刻掩模图案。 然后用导电材料填充凹槽图案和孔，以形成用于连接栅电极的局部互连层。

公开(公告)号：US20080042240A1

公开(公告)日：2008-02-21

申请号：US11976251

申请日：2007-10-23

Applicant: Yeol Jon ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

Inventor： Yeol Jon ,  Chung-Ki Min ,  Yong-Sun Ko ,  Kyung-Hyun Kim

IPC: H01L29/00

CPC classification number: H01L27/10894 ,  H01L27/10852

Abstract: Provided is a semiconductor device including a vertically oriented capacitor extending above the substrate surface and a method of manufacturing such devices in which cell, peripheral and boundary areas between the cell and peripheral areas are defined on a semiconductor substrate. Capacitors are formed in the cell area, a mold pattern is provided in the peripheral areas and an elongated dummy pattern is provided in the boundary areas. The dummy pattern includes a boundary opening in which a thin layer is formed on the elongated inner sidewalls and on the exposed portion of the substrate during formation of the lower electrode. A mold pattern and lower electrode structures having substantially the same height are then formed area so that subsequent insulation interlayer(s) exhibit a generally planar surface, i.e., have no significant step difference between the cell areas and the peripheral areas.

Abstract translation: 提供一种包括在基板表面上方延伸的垂直取向的电容器的半导体器件以及制造这样的器件的方法，其中在半导体衬底上限定了单元和外围区域之间的单元，外围和边界区域。 电容器形成在电池区域中，在外围区域设置模具图案，并且在边界区域中设置细长的虚拟图案。 虚拟图案包括边界开口，其中在形成下电极期间在细长的内侧壁上和在基板的暴露部分上形成薄层。 然后形成具有基本上相同高度的模具图案和下部电极结构，使得随后的绝缘中间层呈现大致平坦的表面，即在电池区域和外围区域之间没有显着的步进差异。

公开(公告)号：US20070298129A1

公开(公告)日：2007-12-27

申请号：US11804588

申请日：2007-05-18

Applicant: Byoung Gwag ,  Young Lee ,  Jin Shin ,  Sung Cho ,  Jae Noh ,  Jae Cho ,  Ki Kim ,  Hyang Lim ,  Jae Lee ,  Han Byun ,  Sun Ko ,  Sun Son ,  Sun Park

Inventor： Byoung Gwag ,  Young Lee ,  Jin Shin ,  Sung Cho ,  Jae Noh ,  Jae Cho ,  Ki Kim ,  Hyang Lim ,  Jae Lee ,  Han Byun ,  Sun Ko ,  Sun Son ,  Sun Park

IPC: A61K33/00 ,  A61K31/196 ,  A61P25/00 ,  A61P25/16 ,  A61P25/28 ,  C07C229/56

CPC classification number: A61K31/137 ,  A61K31/195 ,  A61K31/24 ,  A61K31/60 ,  A61K33/00 ,  A61K45/06 ,  A61K2300/00

Abstract: The present invention relates to 2-hydroxy-alkylamino-benzoic acid derivatives and to a combination of cell necrosis inhibitor and lithium, process for the preparation of the derivatives or the combination, pharmaceutical formulation containing the derivatives or the combination, and use of the derivatives or the combination by either concomitant or sequential administration for improvement of treatment of neuronal death or neurological dysfunction. The derivatives and the combination of the present invention are useful for treating neurological diseases, such as amyotrophic lateral sclerosis (ALS, Lou Gehrig's disease), spinal muscular atrophy, Alzheimer's disease, Parkinson's disease, Huntington's disease, stroke, traumatic brain injury or spinal cord injury; and for treating ocular diseases such as glaucoma, diabetic retinopathy or macular degeneration.

Abstract translation: 本发明涉及2-羟基 - 烷基氨基 - 苯甲酸衍生物和细胞坏死物抑制剂与锂的组合，制备衍生物或组合的方法，含有衍生物或组合的药物制剂及其衍生物的用途 或通过伴随或连续施用来改善神经元死亡或神经功能障碍的治疗的组合。 本发明的衍生物和组合可用于治疗神经系统疾病，例如肌萎缩性侧索硬化（ALS，Lou Gehrig's disease），脊髓性肌萎缩症，阿尔茨海默氏病，帕金森病，亨廷顿病，中风，创伤性脑损伤或脊髓 伤害 并用于治疗眼部疾病如青光眼，糖尿病性视网膜病变或黄斑变性。

公开(公告)号：US20070131818A1

公开(公告)日：2007-06-14

申请号：US11701588

申请日：2007-02-02

Applicant: Sun Ko

Inventor： Sun Ko

IPC: B65H16/06

CPC classification number: A47K10/40 ,  B65H16/005 ,  B65H2301/41308 ,  B65H2301/41346 ,  B65H2402/43 ,  B65H2402/5156 ,  B65H2402/542 ,  B65H2701/18484

Abstract: A device for holding a roll of material surrounding a core includes a mount with two arms, each having a retractable catch. The retractable catch includes a contoured end, optionally substantially hemispheric, that transmits a radial force on the core to cause the catch to retract. In an optional embodiment, the catch is part of a catch assembly including a spring biasing the catch perpendicular to the arms and toward the core and an annular retainer that holds the catch to the arms.

Abstract translation: 用于保持围绕芯的材料卷的装置包括具有两个臂的支架，每个臂具有可缩回的卡扣。 可伸缩卡扣包括可选地基本上半球形的轮廓端，其将径向力传递到芯上以使卡扣缩回。 在可选的实施例中，锁扣是捕捉组件的一部分，其包括垂直于臂并朝向芯的偏置锁的弹簧和将卡扣保持在臂上的环形保持器。

公开(公告)号：US20060287208A1

公开(公告)日：2006-12-21

申请号：US11467736

申请日：2006-08-28

Applicant: Kwang-Wook Lee ,  In-Seak Hwang ,  Keum-Joo Lee ,  Chang-Lyong Song ,  Yong-Sun Ko ,  Kui-Jong Baek ,  Woong Han

Inventor： Kwang-Wook Lee ,  In-Seak Hwang ,  Keum-Joo Lee ,  Chang-Lyong Song ,  Yong-Sun Ko ,  Kui-Jong Baek ,  Woong Han

IPC: C11D7/32

CPC classification number: H01L21/02071 ,  C11D3/0084 ,  C11D7/3281 ,  C11D11/0047 ,  C23G1/106

Abstract: A corrosion-inhibiting cleaning composition for semiconductor wafer processing includes hydrogen peroxide at a concentration in a range from about 0.5 wt % to about 5 wt %, sulfuric acid at a concentration in a range from about 1 wt % to about 10 wt %, hydrogen fluoride at a concentration in a range from about 0.01 wt % to about 1 wt %; an azole at a concentration in a range from about 0.1 wt % to about 5 wt % and deionized water. The azole operates to inhibit corrosion of a metal layer being cleaned by chelating with a surface of the metal layer during a cleaning process.

Abstract translation: 用于半导体晶片处理的腐蚀抑制清洁组合物包括浓度在约0.5重量％至约5重量％范围内的浓度在约1重量％至约10重量％范围内的硫酸，氢气 浓度在约0.01重量％至约1重量％范围内的氟化物; 浓度在约0.1重量％至约5重量％范围内的唑类和去离子水。 在清洁过程中，唑类用于通过与金属层的表面螯合来抑制被清洁的金属层的腐蚀。