Method for communicating plural signals generated at a source to a remote destination through a single wire
    1.
    发明授权
    Method for communicating plural signals generated at a source to a remote destination through a single wire 有权
    用于通过单根线将在源处产生的多个信号传送到远程目的地的方法

    公开(公告)号:US07711869B1

    公开(公告)日:2010-05-04

    申请号:US11960759

    申请日:2007-12-20

    IPC分类号: G06F3/00 G06F11/00

    CPC分类号: G06F1/24

    摘要: A system having a processor, a printed circuit board, and an adapter board, coupled to the processor through the printed circuit board. The adapter board provides a first signal having a first state when the adapter board is in a proper operating condition and a second state when the adapter board is in an improper condition. The adapter board produces a second signal having the second state for less than a predetermined time when an adapter board requires a reset signal from the processor. The adapter board combines the first signal with the second signal a single signal fed to the processor through the printed circuit board. When the processor detects that the single signal is in the second state for a time less than the predetermined period of time, the process interprets the single signal as indicating the adapter board requires a reset.

    摘要翻译: 具有经由印刷电路板耦合到处理器的处理器,印刷电路板和适配器板的系统。 当适配器板处于正确的操作状态时,适配器板提供具有第一状态的第一信号,并且当适配器板处于不正确状态时提供第二状态。 当适配器板需要来自处理器的复位信号时,适配器板产生具有第二状态的第二信号小于预定时间。 适配器板将第一信号与第二信号组合,通过印刷电路板将单个信号馈送到处理器。 当处理器检测到单个信号处于小于预定时间段的时间的第二状态时,该过程将单个信号解释为指示适配器板需要复位。

    Deriving corresponding signals
    2.
    发明授权
    Deriving corresponding signals 有权
    派生相应的信号

    公开(公告)号:US07383373B1

    公开(公告)日:2008-06-03

    申请号:US11386029

    申请日:2006-03-21

    CPC分类号: G06F1/04 H03K17/002

    摘要: Apparatus used in deriving corresponding signals includes first and second circuitry. The first circuitry derives, from a source-terminated first signal driven from a Peripheral Control Interface (PCI) Express compatible source, an AC-coupled second signal. The second circuitry derives, from the AC-coupled second signal, a destination-terminated DC biased third signal that drives a pseudo-emitter-coupled logic (PECL) compatible receiver.

    摘要翻译: 用于导出相应信号的装置包括第一和第二电路。 第一个电路源自从外围控制接口(PCI)Express兼容源驱动的源端接的第一个信号,AC耦合的第二个信号。 第二电路从交流耦合的第二信号得出驱动伪发射极耦合逻辑(PECL)兼容接收机的目的地端接的DC偏置的第三信号。

    Midplane-less data storage enclosure
    3.
    发明授权
    Midplane-less data storage enclosure 有权
    无中间数据存储机柜

    公开(公告)号:US07145776B2

    公开(公告)日:2006-12-05

    申请号:US10745100

    申请日:2003-12-22

    IPC分类号: H05K5/00

    摘要: Described is a midplane-less data storage enclosure having a control board module with an electrical connector and a bulkhead assembly with a plurality of spaced-apart disk-drive guides coupled to a bulkhead. The disk-drive guides and bulkhead together define a plurality of disk-drive slots. The bulkhead has connected thereto a plurality of first electrical connectors and a second electrical connector in electrical communication with each of the first electrical connectors. Each slot slidably receives a storage disk drive such that the storage disk drive electrically connects to one of the first electrical connectors. The second electrical connector is electrically connected to the connector of the control board module so that each storage disk drive connected to one of the first electrical connectors is in electrical communication with the control board module.

    摘要翻译: 描述了一种具有电连接器的控制板模块和具有耦合到隔板的多个间隔开的盘驱动引导件的隔板组件的无中平面数据存储外壳。 磁盘驱动器引导件和隔板一起限定多个磁盘驱动器槽。 隔板连接有多个第一电连接器和与每个第一电连接器电连通的第二电连接器。 每个槽可滑动地接收存储盘驱动器,使得存储盘驱动器电连接到第一电连接器中的一个。 第二电连接器电连接到控制板模块的连接器,使得连接到第一电连接器之一的每个存储盘驱动器与控制板模块电连通。

    Single printed circuit board configuration for a data storage system
    6.
    发明授权
    Single printed circuit board configuration for a data storage system 有权
    用于数据存储系统的单一印刷电路板配置

    公开(公告)号:US07660334B1

    公开(公告)日:2010-02-09

    申请号:US10878075

    申请日:2004-06-28

    IPC分类号: H04J3/02

    摘要: A data storage system includes a first storage processor for storing and retrieving data from a data storage array for at least one host computer; a second storage processor, coupled to the first storage processor by a communication link, for storing and retrieving data from the data storage array for the at least one host computer; a number M of multiplexers, M being greater than one, each of the multiplexers being coupled to the first storage processor and the second storage processor for receiving data signals from the first storage processor and the second storage processor and transmitting the data signals to a disk drive device; a number A of arbiters, each being coupled to the first storage processor, the second storage processor and a number N of the plurality of multiplexers, for receiving arbiter control signals from the first storage processor and the second storage processor and transmitting multiplexer control signals to each of the number N of the plurality of multiplexers; and a midplane device coupled between the plurality of multiplexers and the data storage array for transferring the data signals from the plurality of multiplexers to the data storage array. The first storage processor, the second storage processor, the plurality of multiplexers, the plurality of arbiters and the midplane are all mounted on a single printed circuit board.

    摘要翻译: 数据存储系统包括:第一存储处理器,用于从用于至少一个主计算机的数据存储阵列中存储和检索数据; 第二存储处理器,通过通信链路耦合到第一存储处理器,用于从用于至少一个主计算机的数据存储阵列存储和检索数据; M个多路复用器,M大于1,每个复用器耦合到第一存储处理器和第二存储处理器,用于从第一存储处理器和第二存储处理器接收数据信号,并将数据信号发送到盘 驱动装置; 仲裁器的数量A,每个仲裁器分别耦合到第一存储处理器,第二存储处理器和多个多路复用器的数目N,用于从第一存储处理器和第二存储处理器接收仲裁器控制信号,并将多路复用器控制信号发送到 所述多个多路复用器的数量N中的每一个; 以及耦合在所述多个多路复用器和所述数据存储阵列之间的中平面设备,用于将所述数据信号从所述多个复用器传送到所述数据存储阵列。 第一存储处理器,第二存储处理器,多个复用器,多个仲裁器和中间板都安装在单个印刷电路板上。

    Highly available dual serial bus architecture
    7.
    发明授权
    Highly available dual serial bus architecture 有权
    高可用的双串行总线架构

    公开(公告)号:US07369380B1

    公开(公告)日:2008-05-06

    申请号:US11431337

    申请日:2006-05-10

    IPC分类号: H02H7/00

    摘要: In a highly available storage system, an enclosure includes first and second power supplies, and first and second controller boards. Each of the first and second controller boards includes first and second serial bus controllers. First and second serial buses are coupled to both of the first and second serial bus controllers on each of the first and second controller boards. The first serial bus is coupled to the first power supply, while the second serial bus coupled to the second power supply. The first and second serial buses are used for exchanging enclosure management and environmental information between the first and second power supplies and the first and second controller boards. The first and second serial buses are coupled to isolation switches so that redundant modules can operate if a serial bus controller fails.

    摘要翻译: 在高度可用的存储系统中,机箱包括第一和第二电源以及第一和第二控制器板。 第一和第二控制器板中的每一个包括第一和第二串行总线控制器。 第一和第二串行总线在第一和第二控制器板中的每一个上耦合到第一和第二串行总线控制器两者。 第一串行总线耦合到第一电源,而第二串​​行总线耦合到第二电源。 第一和第二串行总线用于在第一和第二电源以及第一和第二控制器板之间交换外壳管理和环境信息。 第一和第二串行总线耦合到隔离开关,以便在串行总线控制器发生故障时冗余模块可以工作。

    Method and system for distributing power in a computer system
    8.
    发明授权
    Method and system for distributing power in a computer system 有权
    在计算机系统中分配电力的方法和系统

    公开(公告)号:US07263569B1

    公开(公告)日:2007-08-28

    申请号:US10955354

    申请日:2004-09-30

    IPC分类号: G06F1/24 G06F1/26 G06F11/00

    CPC分类号: G06F1/26 G06F13/4081

    摘要: An apparatus for distributing power in a computer system includes a power supply device; a processing device including a CPU module and a plurality of I/O modules; and an insert line coupled between the power supply and the processing device. The insert line is connected to each of the CPU module and the plurality of I/O modules before terminating at a ground connection within the processing device. The CPU module and the plurality of I/O modules are powered by the power supply. When one of the CPU module and the plurality of I/O modules is removed from the processing device, the power supply senses that the insert line is no longer grounded, and removes power from the CPU module and the plurality of I/O modules.

    摘要翻译: 一种用于在计算机系统中分配电力的装置包括:电源装置; 处理装置,包括CPU模块和多个I / O模块; 以及耦合在所述电源和所述处理装置之间的插入线。 插入线在终止处理装置内的接地连接之前连接到CPU模块和多个I / O模块中的每一个。 CPU模块和多个I / O模块由电源供电。 当从处理装置中取出CPU模块和多个I / O模块中的一个时,电源检测到插入线不再接地,并且从CPU模块和多个I / O模块中移除电力。

    Data storage system with improved serviceability features
    9.
    发明授权
    Data storage system with improved serviceability features 有权
    数据存储系统具有改进的可维护性特征

    公开(公告)号:US07254016B1

    公开(公告)日:2007-08-07

    申请号:US10853746

    申请日:2004-05-25

    IPC分类号: H05K5/00 H05K7/00

    CPC分类号: G06F1/3203

    摘要: A data storage system having an interconnect, storage devices coupled to a first side of the interconnect, and a processing subsystem coupled to a second side of the interconnect that is substantially opposite the first side. The method involves a user (e.g., a customer) receiving a fault signal from the data storage system (e.g., an email notification, a GUI message, an LED pattern, etc.), identifying a component of the data storage system as faulty in response to receiving the fault signal, and replacing the identified component with a new component. In general, the user replaces the identified component in a hot-swapping manner when the identified component is a storage device or a power supply. Additionally, the user replaces the identified component in a powered-down manner when the identified component is a portion of a storage processing circuit (e.g., an internal fan, a memory circuit, a storage processing circuit, etc.).

    摘要翻译: 具有互连的数据存储系统,耦合到所述互连的第一侧的存储设备,以及耦合到所述互连的第二侧的处理子系统,其基本上与所述第一侧相对。 该方法涉及从数据存储系统(例如,电子邮件通知,GUI消息,LED图案等)接收故障信号的用户(例如,客户),将数据存储系统的组件识别为错误 响应于接收到故障信号,并用新的组件替换所识别的组件。 通常,当识别的组件是存储设备或电源时,用户以热插拔方式替换所识别的组件。 此外,当所识别的组件是存储处理电路(例如,内部风扇,存储器电路,存储处理电路等)的一部分时,用户以断电方式替换所识别的组件。