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公开(公告)号：US09588155B2
公开(公告)日：2017-03-07
申请号：US14516555
申请日：2014-10-16
IPC分类号： G01R31/02 , G01R19/165 , B60R21/01
CPC分类号： G01R19/16571 , B60R21/01 , B60R2021/01068
摘要： Threshold detection for load current on a bus involves generating an output current representative of the load current using a transconductance circuit, sampling the output current during a quiescent phase of the bus to produce a sample current, generating a compensation current that is proportional to the transconductance gain associated with the transconductance circuit, where the compensation current is a function of the sample current, combining the output current, the sample current, the compensation current, and a reference current representative of a threshold value for the load current to produce a combined current, and using a discriminator during an active phase of the bus to output a first value when the sum current exceeds the threshold value and a second value when the combined current is less than the threshold value.
摘要翻译： 总线上负载电流的阈值检测包括使用跨导电路产生代表负载电流的输出电流，在总线的静止阶段对输出电流进行采样以产生采样电流，产生与跨导成比例的补偿电流 与跨导电路相关联的增益，其中补偿电流是采样电流的函数，组合输出电流，采样电流，补偿电流和代表负载电流的阈值的参考电流以产生组合电流 并且当总和电流超过阈值时，在总线的有效相位期间使用鉴别器输出第一值，当组合电流小于阈值时，输出第二值。
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公开(公告)号：US09353017B2
公开(公告)日：2016-05-31
申请号：US14307472
申请日：2014-06-17
CPC分类号： C05F3/02 , G05F3/02 , H03M1/12 , H03M1/48 , Y02A40/206 , Y02P20/145
摘要： A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.
摘要翻译： 在IC中修整电流源的方法包括从外部电源导出参考电压，以及跨接在待修整电流上的外部参考电阻产生测量电压。 片上ADC用于提供相应的数字参考和数字测量信号。 数字比较器比较数字信号并提供数字微调信号，用于调整待修整的电流，直到数字测量信号等于可接受公差内的数字参考信号。 ADC中的增益和偏移误差取消，不影响校正操作的校准。
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公开(公告)号：US20160109489A1
公开(公告)日：2016-04-21
申请号：US14516555
申请日：2014-10-16
IPC分类号： G01R19/00
CPC分类号： G01R19/16571 , B60R21/01 , B60R2021/01068
摘要： Threshold detection for load current on a bus involves generating an output current representative of the load current using a transconductance circuit, sampling the output current during a quiescent phase of the bus to produce a sample current, generating a compensation current that is proportional to the transconductance gain associated with the transconductance circuit, where the compensation current is a function of the sample current, combining the output current, the sample current, the compensation current, and a reference current representative of a threshold value for the load current to produce a combined current, and using a discriminator during an active phase of the bus to output a first value when the sum current exceeds the threshold value and a second value when the combined current is less than the threshold value.
摘要翻译： 总线上负载电流的阈值检测包括使用跨导电路产生代表负载电流的输出电流，在总线的静止阶段对输出电流进行采样以产生采样电流，产生与跨导成比例的补偿电流 与跨导电路相关联的增益，其中补偿电流是采样电流的函数，组合输出电流，采样电流，补偿电流和代表负载电流的阈值的参考电流以产生组合电流 并且当总和电流超过阈值时，在总线的有效相位期间使用鉴别器输出第一值，当组合电流小于阈值时，输出第二值。
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公开(公告)号：US20160236637A1
公开(公告)日：2016-08-18
申请号：US14624591
申请日：2015-02-18
IPC分类号： B60R21/013 , H03K17/94
CPC分类号： B60R21/01336 , B60R21/0173 , B60R2021/01129 , B60R2021/01177 , B60R2021/01286
摘要： A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.
摘要翻译： 用于检测第一和第二输入信号之间的失配的系统包括第一和第二模数转换器，时分复用电路，第一和第二处理器，时分解复用电路和选通电路。 第一处理器包括第一正弦滤波器，第一微调器，第一无限脉冲响应（IIR）滤波器和第一高通滤波器（HPF）。 第二处理器包括第二sinc滤波器，第二IIR滤波器和第二HPF。 第二IIR滤波器和第二HPF的带宽大于第一IIR滤波器和第一HPF的带宽。 第一IIR滤波器和第一HPF的传递函数使用浮点系数和第二IIR滤波器的传递函数，并且第二HPF使用作为2的整数倍的系数。
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公开(公告)号：US20150362942A1
公开(公告)日：2015-12-17
申请号：US14307472
申请日：2014-06-17
CPC分类号： C05F3/02 , G05F3/02 , H03M1/12 , H03M1/48 , Y02A40/206 , Y02P20/145
摘要： A method of trimming a current source in an IC includes deriving a reference voltage from an external supply, and developing a measurement voltage across an external reference resistance receiving the current to be trimmed. An on-chip ADC is used to provide corresponding digital reference and digital measurement signals. A digital comparator compares the digital signals and provides a digital trim signal, which is used to adjust the current to be trimmed until the digital measurement signal is equal to the digital reference signal within an acceptable tolerance. Gain and offset errors in the ADC cancel and do not affect the calibration of the trim operation.
摘要翻译： 在IC中修整电流源的方法包括从外部电源导出参考电压，以及跨接在待修整电流上的外部参考电阻产生测量电压。 片上ADC用于提供相应的数字参考和数字测量信号。 数字比较器比较数字信号并提供数字微调信号，用于调整要修整的电流，直到数字测量信号等于可接受公差内的数字参考信号。 ADC中的增益和偏移误差取消，不影响校正操作的校准。
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6.发明申请METHOD AND SYSTEM TO COMPENSATE FOR TEMPERATURE AND PRESSURE IN PIEZO RESISTIVE DEVICES 有权在PIEZO电阻器件中补偿温度和压力的方法和系统公开(公告)号：US20140182353A1
公开(公告)日：2014-07-03
申请号：US14197221
申请日：2014-03-05
IPC分类号： G01L27/00
CPC分类号： G01L27/005 , G01L9/065 , G01L27/002
摘要： A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.
摘要翻译： 一种用于校准具有两个变量的非线性传感器的压电器件中的温度和压力的方法和系统，其中压电电阻器件例如压力传感器系统中使用的压阻式换能器（PRT）被校准以计算实际/ 环境温度和压力即使PRT阻抗相对于压力不平衡。
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7.发明授权Method and system to compensate for temperature and pressure in piezo resistive devices 有权用于补偿压电器件温度和压力的方法和系统公开(公告)号：US08701460B2
公开(公告)日：2014-04-22
申请号：US13077963
申请日：2011-03-31
IPC分类号： G01L27/00
CPC分类号： G01L27/005 , G01L9/065 , G01L27/002
摘要： A method and system to calibrate temperature and pressure in piezo resistive devices for non-linear sensors having two variables, where a piezo resistive device such as a piezo resistive transducer (PRT) used for example in a pressure sensor system is calibrated to calculate actual/ambient temperature and pressure even though the PRT impedance is unbalanced relative to pressure.
摘要翻译： 一种用于校准具有两个变量的非线性传感器的压电器件中的温度和压力的方法和系统，其中压电电阻器件例如压力传感器系统中使用的压阻式换能器（PRT）被校准以计算实际/ 环境温度和压力即使PRT阻抗相对于压力不平衡。
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公开(公告)号：US08487683B1
公开(公告)日：2013-07-16
申请号：US13356610
申请日：2012-01-23
IPC分类号： H03K5/13
CPC分类号： H03K5/13
摘要： A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals.
摘要翻译： 用于产生多相不重叠时钟信号的电路包括从输入时钟信号产生第一和第二时钟信号的移位寄存器。 第一和第二电路模块分别使用第一和第二时钟信号以及第一和第二反馈信号产生对应的第一和第二中间信号。 第一和第二中间信号至少是预定的最小时间差不重叠。 第一和第二中间信号被多路复用以产生输出信号。 输出信号被延迟第一预定时间以产生第一延迟信号。 第一延迟信号被延迟第二预定时间以产生第二延迟信号。 第二延迟信号被解复用以产生第一和第二反馈信号，并且第一延迟信号被去多路复用以产生一组多相不重叠的时钟信号。
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公开(公告)号：US20130187696A1
公开(公告)日：2013-07-25
申请号：US13356610
申请日：2012-01-23
IPC分类号： H03K3/00
CPC分类号： H03K5/13
摘要： A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals.
摘要翻译： 用于产生多相不重叠时钟信号的电路包括从输入时钟信号产生第一和第二时钟信号的移位寄存器。 第一和第二电路模块分别使用第一和第二时钟信号以及第一和第二反馈信号产生对应的第一和第二中间信号。 第一和第二中间信号至少是预定的最小时间差不重叠。 第一和第二中间信号被多路复用以产生输出信号。 输出信号被延迟第一预定时间以产生第一延迟信号。 第一延迟信号被延迟第二预定时间以产生第二延迟信号。 第二延迟信号被解复用以产生第一和第二反馈信号，并且第一延迟信号被去多路复用以产生一组多相不重叠的时钟信号。
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公开(公告)号：US09643558B2
公开(公告)日：2017-05-09
申请号：US14624591
申请日：2015-02-18
IPC分类号： B60R21/013 , H03K17/94 , G06F11/16 , B60R21/0132 , B60R21/017 , B60R21/01
CPC分类号： B60R21/01336 , B60R21/0173 , B60R2021/01129 , B60R2021/01177 , B60R2021/01286
摘要： A system for detecting a mismatch between first and second input signals includes first and second analog-to-digital converters, a time-division multiplexing circuit, first and second processors, a time-division de-multiplexing circuit, and a gating circuit. The first processor includes a first sinc filter, a first trimmer, a first infinite impulse response (IIR) filter, and a first high pass filter (HPF). The second processor includes a second sinc filter, a second IIR filter, and a second HPF. A bandwidth of the second IIR filter and the second HPF is greater than a bandwidth of the first IIR filter and the first HPF. A transfer function of the first IIR filter and the first HPF uses floating-point coefficients and a transfer function of the second IIR filter and the second HPF uses coefficients that are an integral power of two.
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