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    Microelectronic fabrication method providing alignment mark and isolation trench of identical depth
    1.
    发明授权
    Microelectronic fabrication method providing alignment mark and isolation trench of identical depth 有权
    提供相同深度的对准标记和隔离沟槽的微电子制造方法

    公开(公告)号：US06500725B1

    公开(公告)日：2002-12-31

    申请号：US09947632

    申请日：2001-09-06

    申请人： Chien-Chuan Chen ,  Chiang-Jen Peng ,  Bin-Chia Su ,  Shu-Huei Suen

    发明人： Chien-Chuan Chen ,  Chiang-Jen Peng ,  Bin-Chia Su ,  Shu-Huei Suen

    IPC分类号： H01L2176

    CPC分类号： H01L23/544 ,  H01L21/76229 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed simultaneously within the substrate an alignment mark and an isolation trench formed employing a single etch method and to an identical depth within the substrate. There is then formed within the isolation trench an isolation region. Finally, there is then further processed the substrate while aligning the substrate while using the alignment mark in conjunction with a minimum of two alignment wavelengths. The method provides for enhanced efficiency when fabricating the microelectronic fabrication. The method contemplates a microelectronic fabrication fabricated employing the method.

    摘要翻译： 在微电子制造的制造方法中，首先提供基板。 然后在衬底内同时形成对准标记和使用单一蚀刻方法形成的隔离沟槽，并在衬底内形成相同的深度。 然后在隔离沟槽内形成隔离区域。 最后，在使用对准标记和最少两个取向波长的同时对准衬底的同时进一步处理衬底。 该方法在制造微电子制造时提供了增强的效率。 该方法考虑使用该方法制造的微电子制造。

    Wafer transfer pod for reducing wafer particulate contamination
    3.
    发明授权
    Wafer transfer pod for reducing wafer particulate contamination 有权
    用于减少晶圆颗粒污染的晶圆转运荚

    公开(公告)号：US08544651B2

    公开(公告)日：2013-10-01

    申请号：US13354969

    申请日：2012-01-20

    申请人： Ying Zhang ,  Tien-Chih Cheng ,  Shu-Huei Suen ,  Yu-Cheng Liu ,  Jian-Huah Chiou

    发明人： Ying Zhang ,  Tien-Chih Cheng ,  Shu-Huei Suen ,  Yu-Cheng Liu ,  Jian-Huah Chiou

    IPC分类号： B65D81/02 ,  B65D81/18

    CPC分类号： H01L21/67386 ,  H01L21/67389

    摘要： A wafer transport pod for storing or transporting semiconductor wafers during semiconductor wafer processing includes a body having a top panel, a bottom panel, a back panel, two side panels and a front panel. The two side panels are configured for receiving the semiconductor wafers therebetween. The two side panels have a plurality of separately hermetically sealed partitions inside the body, any two of the sealed partitions for sealing a wafer therebetween and for preventing wafer contamination. The front panel provides ingress and egress for the semiconductor wafers to and from the wafer transport pod.

    摘要翻译： 用于在半导体晶片处理期间存储或传输半导体晶片的晶片传输盒包括具有顶板，底板，后面板，两个侧板和前面板的主体。 两个侧面板被构造成用于接收它们之间的半导体晶片。 两个侧面板在主体内具有多个单独的气密密封的隔板，用于密封其间的晶片的任何两个密封隔板和用于防止晶片污染。 前面板为半导体晶片提供进出晶片传输盒的入口和出口。

    WAFER TRANSFER POD FOR REDUCING WAFER PARTICULATE CONTAMINATION
    4.
    发明申请
    WAFER TRANSFER POD FOR REDUCING WAFER PARTICULATE CONTAMINATION 有权
    用于减少颗粒污染的WAFER转移池

    公开(公告)号：US20130186803A1

    公开(公告)日：2013-07-25

    申请号：US13354969

    申请日：2012-01-20

    申请人： Ying ZHANG ,  Tien-Chih CHENG ,  Shu-Huei SUEN ,  Yu-Cheng LIU ,  Jian-Huah CHIOU

    发明人： Ying ZHANG ,  Tien-Chih CHENG ,  Shu-Huei SUEN ,  Yu-Cheng LIU ,  Jian-Huah CHIOU

    IPC分类号： H01L21/68 ,  H01L21/673

    CPC分类号： H01L21/67386 ,  H01L21/67389

    摘要： A wafer transport pod for storing or transporting semiconductor wafers during semiconductor wafer processing includes a body having a top panel, a bottom panel, a back panel, two side panels and a front panel. The two side panels are configured for receiving the semiconductor wafers therebetween, The two side panels have a plurality of separately hermetically sealed partitions inside the body, any two of the sealed partitions for sealing a wafer therebetween and for preventing wafer contamination. The front panel provides ingress and egress for the semiconductor wafers to and from the wafer transport pod.

    摘要翻译： 用于在半导体晶片处理期间存储或传输半导体晶片的晶片传输盒包括具有顶板，底板，后面板，两个侧板和前面板的主体。 两个侧板被构造成用于在其间接收半导体晶片。两个侧板在主体内部具有多个分开的气密密封的隔板，用于密封其间的晶片的任何两个密封隔板和用于防止晶片污染。 前面板为半导体晶片提供进出晶片传输盒的入口和出口。

    Two step trench definition procedure for formation of a dual damascene opening in a stack of insulator layers
    5.
    发明授权
    Two step trench definition procedure for formation of a dual damascene opening in a stack of insulator layers 失效
    用于在一叠绝缘体层中形成双镶嵌开口的两阶沟槽定义程序

    公开(公告)号：US07001836B2

    公开(公告)日：2006-02-21

    申请号：US10808802

    申请日：2004-03-25

    申请人： Fu-Kai Yang ,  Shu-Huei Suen

    发明人： Fu-Kai Yang ,  Shu-Huei Suen

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76808 ,  H01L21/76813

    摘要： A process for defining a dual damascene opening in a stack of insulator layers to expose a portion of a top surface of an underlying conductive structure, has been developed. The process features a two step procedure for removal of insulator stop layers, wherein the stop layers are employed to allow selective dry etch procedures to be used for definition of both the via opening component and the trench shape component of the dual damascene opening. After definition of the via opening, terminating at the top surface of an underlying, first silicon nitride stop layer, a photoresist shape is used as an etch mask to allow a dry etch procedure to define a trench shape in a top portion of an insulator stack, with the dry etch procedure terminating at the top surface of an overlying second silicon nitride stop layer. The dry etch procedure also results in formation of a photoresist plug in the via hole, located on an underlying, first silicon nitride stop layer. The portion of the second silicon nitride stop layer exposed in the trench shape opening is next selectively removed via a first procedure of the two step, dry etch removal procedure, followed by removal of the trench shape defining photoresist shape and of the photoresist plug. Another dry etch procedure, the second step of the two step dry etch removal procedure, is next performed to selectively remove the portion of underlying, first silicon nitride stop layer exposed in the via opening, resulting in exposure of a portion of the top surface of the conductive structure. The two step, stop layer removal procedure reduces the level of insulator corner rounding at the top of the dual damascene opening, while also reducing damage to the top surface of the underlying conductive structure, exposed at the bottom of the dual damascene opening.

    摘要翻译： 已经开发了用于在绝缘体层堆叠中限定双镶嵌开口以暴露下面的导电结构的顶表面的一部分的方法。 该方法具有用于去除绝缘体停止层的两步程序，其中使用停止层以允许选择性干法蚀刻程序用于双镶嵌开口的通孔开口部件和沟槽形状部件的定义。 在通孔开口的定义之后，终止在下面的第一氮化硅阻挡层的顶表面处，使用光致抗蚀剂形状作为蚀刻掩模，以允许干蚀刻工艺在绝缘体堆叠的顶部中限定沟槽形状 ，其中干蚀刻程序终止于覆盖的第二氮化硅阻挡层的顶表面。 干蚀刻程序还导致在通孔中形成位于下面的第一氮化硅阻挡层上的光致抗蚀剂插塞。 接下来通过两步干法蚀刻去除步骤的第一步骤，然后去除限定光致抗蚀剂形状的沟槽形状和光致抗蚀剂插塞，选择性地去除在沟槽形开口中暴露的第二氮化硅阻挡层的部分。 接下来执行另一干法蚀刻步骤，即两步干法蚀刻去除步骤的第二步骤，以选择性地去除在通孔开口中暴露的下面的第一氮化硅阻挡层的部分，导致暴露在顶部表面的一部分 导电结构。 两步骤，停止层去除程序降低了在双镶嵌开口顶部的绝缘子角圆角的水平，同时还减少了暴露在双镶嵌开口底部的下面的导电结构的顶表面的损坏。

    TWO STEP TRENCH DEFINITION PROCEDURE FOR FORMATION OF A DUAL DAMASCENE OPENING IN A STACK OF INSULATOR LAYERS
    8.
    发明申请
    TWO STEP TRENCH DEFINITION PROCEDURE FOR FORMATION OF A DUAL DAMASCENE OPENING IN A STACK OF INSULATOR LAYERS 失效
    用于在绝缘层堆叠中形成双重大气开放的两步骤放热定义步骤

    公开(公告)号：US20050215051A1

    公开(公告)日：2005-09-29

    申请号：US10808802

    申请日：2004-03-25

    申请人： Fu-Kai Yang ,  Shu-Huei Suen

    发明人： Fu-Kai Yang ,  Shu-Huei Suen

    IPC分类号： H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/76808 ,  H01L21/76813

    摘要： A process for defining a dual damascene opening in a stack of insulator layers to expose a portion of a top surface of an underlying conductive structure, has been developed. The process features a two step procedure for removal of insulator stop layers, wherein the stop layers are employed to allow selective dry etch procedures to be used for definition of both the via opening component and the trench shape component of the dual damascene opening. After definition of the via opening, terminating at the top surface of an underlying, first silicon nitride stop layer, a photoresist shape is used as an etch mask to allow a dry etch procedure to define a trench shape in a top portion of an insulator stack, with the dry etch procedure terminating at the top surface of an overlying second silicon nitride stop layer. The dry etch procedure also results in formation of a photoresist plug in the via hole, located on an underlying, first silicon nitride stop layer. The portion of the second silicon nitride stop layer exposed in the trench shape opening is next selectively removed via a first procedure of the two step, dry etch removal procedure, followed by removal of the trench shape defining photoresist shape and of the photoresist plug. Another dry etch procedure, the second step of the two step dry etch removal procedure, is next performed to selectively remove the portion of underlying, first silicon nitride stop layer exposed in the via opening, resulting in exposure of a portion of the top surface of the conductive structure. The two step, stop layer removal procedure reduces the level of insulator corner rounding at the top of the dual damascene opening, while also reducing damage to the top surface of the underlying conductive structure, exposed at the bottom of the dual damascene opening.

    摘要翻译： 已经开发了用于在绝缘体层堆叠中限定双镶嵌开口以暴露下面的导电结构的顶表面的一部分的方法。 该方法具有用于去除绝缘体停止层的两步程序，其中使用停止层以允许选择性干法蚀刻程序用于双镶嵌开口的通孔开口部件和沟槽形状部件的定义。 在通孔开口的定义之后，终止在下面的第一氮化硅阻挡层的顶表面处，使用光致抗蚀剂形状作为蚀刻掩模，以允许干蚀刻工艺在绝缘体堆叠的顶部中限定沟槽形状 ，其中干蚀刻程序终止于覆盖的第二氮化硅阻挡层的顶表面。 干蚀刻程序还导致在通孔中形成位于下面的第一氮化硅阻挡层上的光致抗蚀剂插塞。 接下来通过两步干法蚀刻去除步骤的第一步骤，然后去除限定光致抗蚀剂形状的沟槽形状和光致抗蚀剂插塞，选择性地去除在沟槽形开口中暴露的第二氮化硅阻挡层的部分。 接下来执行另一干法蚀刻步骤，即两步干法蚀刻去除步骤的第二步骤，以选择性地去除在通孔开口中暴露的下面的第一氮化硅阻挡层的部分，导致暴露在顶部表面的一部分 导电结构。 两步骤，停止层去除程序降低了在双镶嵌开口顶部的绝缘子角圆角的水平，同时还减少了暴露在双镶嵌开口底部的下面的导电结构的顶表面的损坏。