知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.019 秒)

    Method of manufacturing a semiconductor device having a one time programmable (OTP) erasable and programmable read only memory (EPROM) cell
    1.
    发明授权
    Method of manufacturing a semiconductor device having a one time programmable (OTP) erasable and programmable read only memory (EPROM) cell 失效
    制造具有一次可编程（OTP）可擦除和可编程只读存储器（EPROM）单元的半导体器件的方法

    公开(公告)号：US07491657B2

    公开(公告)日：2009-02-17

    申请号：US11681429

    申请日：2007-03-02

    申请人： Ki-Hyung Lee ,  Seung-Han Yoo

    发明人： Ki-Hyung Lee ,  Seung-Han Yoo

    IPC分类号： H01L21/70

    CPC分类号： H01L27/115 ,  H01L27/11526 ,  H01L27/11546

    摘要： Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film Is interposed between the gate and the PEOX film in the main chip region.

    摘要翻译： 提供了一种可擦除和可编程的只读存储器（EPROM）器件，其中等离子体增强氧化物（PEOX）膜覆盖单个多时间可编程（OTP）单元中的浮动栅极的上表面，以及制造半导体器件的方法 有同样的 半导体器件包括具有OTP单元区域的衬底，在其上形成用于制造OTP单元晶体管的浮置栅极和形成晶体管的栅极的主芯片区域。 在OTP单元区域和主芯片区域上形成PEOX膜。 PEOX膜在关闭状态下覆盖浮动栅极并且将栅极覆盖预定距离。 在主芯片区域中的栅极和PEOX膜之间插入氮氧化硅（SiON）膜。

    EEPROM Having Single Gate Structure and Method of Operating the Same
    2.
    发明申请
    EEPROM Having Single Gate Structure and Method of Operating the Same 有权
    具有单门结构的EEPROM及其操作方法

    公开(公告)号：US20080002476A1

    公开(公告)日：2008-01-03

    申请号：US11682619

    申请日：2007-03-06

    申请人： Seung-Han Yoo ,  Hoon Chang

    发明人： Seung-Han Yoo ,  Hoon Chang

    IPC分类号： G11C16/04 ,  G11C11/34 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11558

    摘要： An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first wells is applied to the second well tap,

    摘要翻译： 电可擦除可编程只读存储器（EEPROM）包括存取晶体管，其具有形成在第一阱中的浮置栅极的相对侧处的浮置栅极和源极/漏极区域，形成在第一阱中的第一阱阱，控制栅极 位于第二区域上，形成在第二区域中的控制栅极的两侧的第一杂质区域和形成在第三区域中的第二阱阱。 为了擦除存储在存储单元中的信息，将预定的擦除电压施加到存取晶体管和第一阱抽头的源极/漏极区域，对第二区域中的第一杂质区域施加接地电压， 大于0V并且小于有源区和第一阱之间的结击穿电压的电压施加到第二阱分接头，

    Semiconductor Devices Including Assymetric Source and Drain Regions Having a Same Width and Related Methods
    5.
    发明申请
    Semiconductor Devices Including Assymetric Source and Drain Regions Having a Same Width and Related Methods 审中-公开
    包括具有相同宽度的比例源和排水区域的半导体器件及相关方法

    公开(公告)号：US20080203497A1

    公开(公告)日：2008-08-28

    申请号：US12032233

    申请日：2008-02-15

    申请人： Young-Chan Lee ,  Seung-Han Yoo ,  Dae-Lim Kang

    发明人： Young-Chan Lee ,  Seung-Han Yoo ,  Dae-Lim Kang

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0847 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

    摘要： A semiconductor device may include an active region of a semiconductor substrate and first and second impurity regions in the active region. The active region may have a first conductivity type, the first and second impurity regions may have a second conductivity type opposite the first conductivity type, and the first and second impurity regions are spaced apart to define a channel region therebetween. A first source/drain region may be provided in the first impurity region, a second source/drain region may be provide in the second impurity region, the first and second source/drain regions may have the second conductivity type, and impurity concentrations of the first and second source/drain regions may be greater than impurity concentrations of the first and second impurity regions. Moreover, the first and second source/drain regions may have a same width in a direction perpendicular with respect to a direction between the first and second source/drain regions, and a distance between the first source/drain region and the channel region may be less than a distance between the second source/drain region and the channel region. In addition, a control gate may be provided on the channel region. Related methods are also discussed.

    摘要翻译： 半导体器件可以包括半导体衬底的有源区和有源区中的第一和第二杂质区。 有源区可以具有第一导电类型，第一和第二杂质区可以具有与第一导电类型相反的第二导电类型，并且第一和第二杂质区间隔开以限定它们之间的沟道区。 第一源极/漏极区域可以设置在第一杂质区域中，第二源极/漏极区域可以在第二杂质区域中提供，第一和第二源极/漏极区域可以具有第二导电类型，并且第 第一和第二源/漏区可以大于第一和第二杂质区的杂质浓度。 此外，第一和第二源极/漏极区域可以在垂直于第一和第二源极/漏极区域之间的方向上具有相同的宽度，并且第一源极/漏极区域和沟道区域之间的距离可以是 小于第二源极/漏极区域和沟道区域之间的距离。 此外，可以在通道区域上设置控制栅极。 还讨论了相关方法。

    Erasable and programmable read only memory (EPROM) cell of an EPROM device and method of manufacturing a semiconductor device having the EPROM cell
    7.
    发明授权
    Erasable and programmable read only memory (EPROM) cell of an EPROM device and method of manufacturing a semiconductor device having the EPROM cell 失效
    EPROM装置的可擦除可编程只读存储器（EPROM）单元和具有EPROM单元的半导体器件的制造方法

    公开(公告)号：US07202522B2

    公开(公告)日：2007-04-10

    申请号：US10973894

    申请日：2004-10-26

    申请人： Ki-Hyung Lee ,  Seung-Han Yoo

    发明人： Ki-Hyung Lee ,  Seung-Han Yoo

    IPC分类号： H01L21/70

    CPC分类号： H01L27/115 ,  H01L27/11526 ,  H01L27/11546

    摘要： Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film is interposed between the gate and the PEOX film in the main chip region.

    摘要翻译： 提供了一种可擦除和可编程的只读存储器（EPROM）器件，其中等离子体增强氧化物（PEOX）膜覆盖单个多时间可编程（OTP）单元中的浮动栅极的上表面，以及制造半导体器件的方法 有同样的 半导体器件包括具有OTP单元区域的衬底，在其上形成用于形成OTP单元晶体管的浮动栅极和形成晶体管的栅极的主芯片区域。 在OTP单元区域和主芯片区域上形成PEOX膜。 PEOX膜在关闭状态下覆盖浮动栅极并且将栅极覆盖预定距离。 在主芯片区域中的栅极和PEOX膜之间插入有氮氧化硅（SiON）膜。

    Semiconductor device having trench isolation structure and method of fabricating the same
    9.
    发明授权
    Semiconductor device having trench isolation structure and method of fabricating the same 有权

    公开(公告)号：US06797579B2

    公开(公告)日：2004-09-28

    申请号：US10755596

    申请日：2004-01-12

    申请人： Seung-Han Yoo ,  Jae-Min Yu ,  Sang-Wook Park ,  Tae-Jung Lee

    发明人： Seung-Han Yoo ,  Jae-Min Yu ,  Sang-Wook Park ,  Tae-Jung Lee

    IPC分类号： H01L21331

    CPC分类号： H01L21/76264 ,  H01L21/76283

    摘要： A semiconductor device having a trench isolation structure and a method of fabricating the same are provided. The device has a trench region and an isolation structure. The trench region is disposed to define an active region at a predetermined region of an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The isolation structure fills an inside of the trench region. The trench region has a deep trench region where the upper silicon layer penetrates to the buried insulating layer and a shallow trench region existing at an outside of the deep trench region. The method of forming a trench region with deep and shallow trench regions includes patterning an upper silicon layer of an SOI substrate. A trench oxide layer and a trench liner are conformally formed on a sidewall and a bottom of the trench region. The trench liner on the bottom of the trench region, the trench oxide layer, and the upper silicon layer are successively patterned to form the deep trench region where the buried insulating layer is exposed. The trench region existing at an outside of the deep trench region corresponds to the shallow trench region.

    Semiconductor device having trench isolation structure and method of fabricating the same
    10.
    发明授权
    Semiconductor device having trench isolation structure and method of fabricating the same 有权
    具有沟槽隔离结构的半导体器件及其制造方法

    公开(公告)号：US06740933B2

    公开(公告)日：2004-05-25

    申请号：US10243019

    申请日：2002-09-13

    申请人： Seung-Han Yoo ,  Jae-Min Yu ,  Sang-Wook Park ,  Tae-Jung Lee

    发明人： Seung-Han Yoo ,  Jae-Min Yu ,  Sang-Wook Park ,  Tae-Jung Lee

    IPC分类号： H01L2701

    CPC分类号： H01L21/76264 ,  H01L21/76283

    摘要： A semiconductor device having a trench isolation structure and a method of fabricating the same are provided. The device has a trench region and an isolation structure. The trench region is disposed to define an active region at a predetermined region of an SOI substrate formed by sequentially stacking a buried insulating layer and an upper silicon layer on a base substrate. The isolation structure fills an inside of the trench region. The trench region has a deep trench region where the upper silicon layer penetrates to the buried insulating layer and a shallow trench region existing at an outside of the deep trench region. The method of forming a trench region with deep and shallow trench regions includes patterning an upper silicon layer of an SOI substrate. A trench oxide layer and a trench liner are conformally formed on a sidewall and a bottom of the trench region. The trench liner on the bottom of the trench region, the trench oxide layer, and the upper silicon layer are successively patterned to form the deep trench region where the buried insulating layer is exposed. The trench region existing at an outside of the deep trench region corresponds to the shallow trench region.

    摘要翻译： 提供了具有沟槽隔离结构的半导体器件及其制造方法。 该器件具有沟槽区域和隔离结构。 沟槽区域被设置为在通过在基底衬底上依次层叠掩埋绝缘层和上硅层而形成的SOI衬底的预定区域处限定有源区。 隔离结构填充沟槽区域的内部。 沟槽区域具有深沟槽区域，其中上硅层穿透到掩埋绝缘层和存在于深沟槽区域外部的浅沟槽区域。 形成具有深和浅沟槽区域的沟槽区域的方法包括图案化SOI衬底的上硅层。 沟槽氧化物层和沟槽衬垫共形地形成在沟槽区域的侧壁和底部上。 沟槽区域底部的沟槽衬垫，沟槽氧化物层和上部硅层被依次构图，以形成埋入绝缘层暴露的深沟槽区域。 存在于深沟槽区域外部的沟槽区域对应于浅沟槽区域。