公开(公告)号：US20090243044A1

公开(公告)日：2009-10-01

申请号：US12382540

申请日：2009-03-18

Applicant: Kouji Tanaka ,  Seiya Isozaki

Inventor： Kouji Tanaka ,  Seiya Isozaki

IPC: H01L29/06 ,  H01L21/78

CPC classification number: H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern.

Abstract translation: 本发明提供一种半导体晶片，其具有划线区域和由划线区域划分的多个元件形成区域，所述半导体晶片包括形成在划线区域中的导电图案; 以及形成在至少导电图案之上的岛状钝化膜，该导电图案在导电图案之中形成或可以暴露于通过沿着划线区域切割半导体晶片而获得的半导体芯片的侧表面，使得岛 形状的钝化膜与导电图案相对。

公开(公告)号：US07994614B2

公开(公告)日：2011-08-09

申请号：US12382540

申请日：2009-03-18

Applicant: Kouji Tanaka ,  Seiya Isozaki

Inventor： Kouji Tanaka ,  Seiya Isozaki

IPC: H01L29/06

CPC classification number: H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern.

Abstract translation: 本发明提供一种半导体晶片，其具有划线区域和由划线区域划分的多个元件形成区域，所述半导体晶片包括形成在划线区域中的导电图案; 以及形成在至少导电图案之上的岛状钝化膜，该导电图案在导电图案之中形成或可以暴露于通过沿着划线区域切割半导体晶片而获得的半导体芯片的侧表面，使得岛 形状的钝化膜与导电图案相对。

公开(公告)号：US5610440A

公开(公告)日：1997-03-11

申请号：US605896

申请日：1996-02-23

Applicant: Seiya Isozaki

Inventor： Seiya Isozaki

IPC: H01L23/40 ,  H01L23/367 ,  H01L23/34

CPC classification number: H01L23/3677 ,  H01L2224/32188 ,  H01L2224/49109 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/16195

Abstract: In a semiconductor device comprising a semiconductor chip, a heat radiation plate mounting the semiconductor chip thereon and having a plurality of rounded corner portions of a first radius, a ceramic substrate for mounting the heat radiation plate, and a metallize pattern formed onto the ceramic substrate for soldering the heat radiation plate onto the ceramic substrate, the metallize pattern has a plurality of rounded corner portions of a second radius. The metallize pattern is larger than the heat radiation plate in area. The first radius is greater than the second radius.

Abstract translation: 在包括半导体芯片的半导体器件中，将半导体芯片安装在其上并具有多个第一半径的圆角部的散热板，用于安装散热板的陶瓷基板和形成在陶瓷基板上的金属化图案 为了将散热板焊接到陶瓷基板上，金属化图案具有第二半径的多个圆角部分。 金属化图案大于区域内的散热板。 第一个半径大于第二个半径。

公开(公告)号：US06608384B2

公开(公告)日：2003-08-19

申请号：US09920754

申请日：2001-08-03

Applicant: Seiya Isozaki

Inventor： Seiya Isozaki

IPC: H01L2352

CPC classification number: H01L24/72 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device includes a bonding-structure for electrically and mechanically bonding a solder ball to the electrode pad. The bonding-structure includes flexible arms that are connected to a common supporting layer that allows a relative displacement of the solder ball in relation to the semiconductor chip. The arms extending in one direction are supported by one supporting layer and the arms extending in an opposite direction are supported by another supporting layer.

Abstract translation: 半导体器件包括用于将焊料球电气和机械地结合到电极焊盘的接合结构。 接合结构包括柔性臂，其连接到允许焊球相对于半导体芯片的相对位移的公共支撑层。 沿一个方向延伸的臂由一个支撑层支撑，并且沿相反方向延伸的臂由另一个支撑层支撑。

公开(公告)号：US06400034B1

公开(公告)日：2002-06-04

申请号：US09614314

申请日：2000-07-12

Applicant: Takehiro Kimura ,  Seiya Isozaki

Inventor： Takehiro Kimura ,  Seiya Isozaki

IPC: H01L2348

CPC classification number: H01L23/3114 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/552 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2224/05647

Abstract: A semiconductor device allowing a finer terminal pitch, a low profile, and easy product inspection is disclosed. A semiconductor device includes a semiconductor chip and a film substrate having the semiconductor chip connected thereon. The film substrate includes an insulating film having a plurality of openings formed in a desired pattern and a wiring layer formed in a chip-connecting surface of the insulating film. Solder balls are each directly bonded to the external connection pads through the openings. The wiring layer includes substrate pads each being connected to the chip pads of the semiconductor chip, and external connection pads each being electrically connected to these substrate pads. The external connection pads are each formed over the openings so that the openings are covered with the external connection pads on the chip-connecting surface of the insulating film, respectively.

Abstract translation: 公开了一种允许更细的端子间距，低轮廓和易于产品检查的半导体器件。 半导体器件包括半导体芯片和连接有半导体芯片的薄膜基板。 薄膜基板包括具有以期望图案形成的多个开口的绝缘膜和形成在绝缘膜的芯片连接表面中的布线层。 焊球通过开口直接接合到外部连接焊盘。 布线层包括各自连接到半导体芯片的芯片焊盘的衬底焊盘，并且每个电连接到这些衬底焊盘的外部连接焊盘。 外部连接焊盘各自形成在开口上，使得开口分别被绝缘膜的芯片连接表面上的外部连接焊盘覆盖。