Access control of memory space in microprocessor systems
    1.
    发明申请
    Access control of memory space in microprocessor systems 审中-公开
    微处理器系统中存储空间的访问控制

    公开(公告)号:US20080077749A1

    公开(公告)日:2008-03-27

    申请号:US11525748

    申请日:2006-09-22

    IPC分类号: G06F12/14

    CPC分类号: G06F12/1416 G06F12/1441

    摘要: A system, computer program product, and method for controlling access to a system memory space are provided. The system includes a processor operable to perform an operation on the memory space and a bus monitor operable to monitor the processor. The bus monitor includes a definition for specifying the operation as either permissible or impermissible for a region of the memory space. The bus monitor is further operable to block the processor from performing the operation in response to the definition specifying the operation as impermissible.

    摘要翻译: 提供了一种用于控制对系统存储器空间的访问的系统,计算机程序产品和方法。 该系统包括可操作以对存储器空间执行操作的处理器和可操作以监视处理器的总线监视器。 总线监视器包括用于将操作指定为存储器空间的区域的允许或不允许的定义。 总线监视器还可操作以响应于将操作指定为不允许的定义来阻止处理器执行操作。

    Microcontroller based flash memory digital controller system
    2.
    发明申请
    Microcontroller based flash memory digital controller system 有权
    基于微控制器的闪存数字控制器系统

    公开(公告)号:US20080040580A1

    公开(公告)日:2008-02-14

    申请号:US11288509

    申请日:2005-11-28

    IPC分类号: G06F9/30

    摘要: A digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug.

    摘要翻译: 一种数字控制系统,包括用于处理定时事件的微控制器,用于解释用户命令的命令解码器,用于处理闪速存储器的突发读取的单独的突发控制器,用于处理对闪存存储器的页写入的程序缓冲器,用于 处理从闪存内核到程序缓冲区的数据传输以及从程序缓冲器到闪存的页写入的地址控制,用于存储和调整存储器控制和存储器测试模式信号的存储器控​​制寄存器块,用于 将地址复用到闪存中并加速程序,擦除和恢复验证,以及用于将数据复用到系统中的I / O Mux模块,以及通用I / O端口(GPIO),可以由 微控制器用于测试和调试。

    Sealed rivetless nut plate
    3.
    发明申请
    Sealed rivetless nut plate 审中-公开
    密封铆钉螺母板

    公开(公告)号:US20070053761A1

    公开(公告)日:2007-03-08

    申请号:US11177371

    申请日:2005-07-08

    IPC分类号: F16B39/28

    摘要: A sealed rivetless nut plate which includes a retainer, a nut and a gasket, all retained in a shroud. The nut includes a threaded throughbore for threadably receiving a fastener as well as a base portion which includes either holes or slots which receive corresponding protrusions or dimples on the retainer. Alternatively, the base portion of the nut can include protrusions or dimples with the retainer providing corresponding holes or slots. Regardless, this feature is configured to provide a specific amount of x-axis and y-axis floatation. The shroud is folded under the retainer, thereby keeping the assembly intact. The shroud allows only a nominal amount of movement of the nut in the vertical axis. Before installation, a mandrel is engaged in assembly. During installation, the mandrel is pulled out, causing a tubular portion of the retainer to expand, against a workpiece, thereby securing the sealed rivetless nut plate in position.

    摘要翻译: 密封的无铆螺母板,其包括保持器,螺母和垫圈,全部保持在护罩中。 螺母包括用于螺纹接纳紧固件的螺纹通孔,以及包括在保持器上接收相应突起或凹坑的孔或槽的基部。 或者,螺母的基部可以包括突起或凹坑,其中保持器提供相应的孔或槽。 无论如何,此功能被配置为提供特定量的x轴和y轴浮动。 护罩被折叠在保持器下方,从而保持组件完好无损。 护罩仅允许螺母在垂直轴上的标称量的运动。 在安装之前,心轴接合在一起。 在安装期间,心轴被拉出,导致保持器的管状部分膨胀到工件上,由此将密封的无铆螺母板固定就位。

    SYSTEMS AND METHODS FOR FILTERING ELECTRONIC COMMUNICATIONS
    4.
    发明申请
    SYSTEMS AND METHODS FOR FILTERING ELECTRONIC COMMUNICATIONS 审中-公开
    用于过滤电子通信的系统和方法

    公开(公告)号:US20110225250A1

    公开(公告)日:2011-09-15

    申请号:US13046585

    申请日:2011-03-11

    IPC分类号: G06F15/16

    CPC分类号: G06Q10/107

    摘要: Systems and methods are provided for filtering electronic communications. One exemplary method includes receiving a first message directed to a user, the first message including a plurality of messaging data; and receiving from the user a selection of the messaging data within the first message. The method further includes adding the selected messaging data to a database in relation to one or more contacts of the user, and receiving a second message directed to the user from at least one of the one or more contacts. The method further includes scanning the second message for the selected messaging data, and filtering, with at least one processor, the second message from delivery to the user if the second message contains the selected messaging data.

    摘要翻译: 提供了用于过滤电子通信的系统和方法。 一种示例性方法包括:接收指向用户的第一消息,所述第一消息包括多个消息传送数据; 以及从所述用户接收所述第一消息内的消息数据的选择。 所述方法还包括将所选择的消息收发数据相对于所述用户的一个或多个联系人添加到数据库,以及从所述一个或多个联系人中的至少一个接收指向所述用户的第二消息。 所述方法还包括扫描所选择的消息收发数据的第二消息,以及如果所述第二消息包含所选择的消息传送数据,则用至少一个处理器对所述第二消息进行过滤以从传送到所述用户。

    Method and apparatus for synchronizing data between different clock domains in a memory controller
    5.
    发明授权
    Method and apparatus for synchronizing data between different clock domains in a memory controller 有权
    用于在存储器控制器中的不同时钟域之间同步数据的方法和装置

    公开(公告)号:US07639764B2

    公开(公告)日:2009-12-29

    申请号:US11206474

    申请日:2005-08-17

    IPC分类号: H04L7/00 H04L7/02

    CPC分类号: G06F13/1689 Y02D10/14

    摘要: The present invention provides method and apparatus for synchronizing data between different clock domains in a memory controller. In one embodiment, a memory controller is provided that includes a command decoder and synchronizing logic. The command decoder is operable to receive a command in accordance with a first clock domain. The synchronizing logic synchronizes the command to a second clock domain that is different from the first clock domain, and includes a first synchronization flop and a second synchronization flop operable to prevent metastability associated with synchronizing the command to the second clock domain.

    摘要翻译: 本发明提供了用于在存储器控制器中的不同时钟域之间同步数据的方法和装置。 在一个实施例中,提供了包括命令解码器和同步逻辑的存储器控​​制器。 命令解码器可操作以接收根据第一时钟域的命令。 同步逻辑将命令同步到与第一时钟域不同的第二时钟域,并且包括第一同步触发器和第二同步触发器,其可操作以防止与将命令同步到第二时钟域相关联的亚稳态。

    Microcontroller based flash memory digital controller system
    6.
    发明授权
    Microcontroller based flash memory digital controller system 有权
    基于微控制器的闪存数字控制器系统

    公开(公告)号:US07600090B2

    公开(公告)日:2009-10-06

    申请号:US11288509

    申请日:2005-11-28

    IPC分类号: G06F12/00

    摘要: A digital control system including a microcontroller for handling timed events, a command decoder for interpreting user commands, a separate burst controller for handling burst reads of the Flash memory, a program buffer for handling page writes to the Flash memory, a page transfer controller for handling data transfers from the Flash core to the program buffer as well as address control for page writes from the program buffer to the Flash memory, a memory control register block for storing and adjusting memory control and memory test mode signals, a memory plane interface for multiplexing addresses into the Flash memory and accelerating program, erase, and recovery verification, and an I/O Mux module for multiplexing data out of the system, and a general purpose I/O port (GPIO) that can be read and written by the microcontroller for use in test and debug.

    摘要翻译: 一种数字控制系统,包括用于处理定时事件的微控制器,用于解释用户命令的命令解码器,用于处理闪速存储器的突发读取的单独的突发控制器,用于处理对闪存存储器的页写入的程序缓冲器,用于 处理从闪存内核到程序缓冲区的数据传输以及从程序缓冲器到闪存的页写入的地址控制,用于存储和调整存储器控制和存储器测试模式信号的存储器控​​制寄存器块,用于 将地址复用到闪存中并加速程序,擦除和恢复验证,以及用于将数据复用到系统中的I / O Mux模块,以及通用I / O端口(GPIO),可以由 微控制器用于测试和调试。

    Command decoder for microcontroller based flash memory digital controller system
    7.
    发明授权
    Command decoder for microcontroller based flash memory digital controller system 有权
    命令解码器,用于基于微控制器的闪存数字控制器系统

    公开(公告)号:US07574611B2

    公开(公告)日:2009-08-11

    申请号:US11288753

    申请日:2005-11-28

    IPC分类号: G06F1/26

    摘要: A command decoder used for a microcontroller based Flash memory digital controller system includes multiple subsystems, including the command decoder, which serves as the main user interface for interpreting commands from a user and managing the priority of commands and command modes. The command decoder also stores crucial information including address, data, opcodes, and various flags registers that are used by other subsystems including the program buffer, burst read module, register block, and microcontroller. In addition, the command decoder contains clock synchronization logic, controls the sleep function of the microcontroller and serves as a test mode controller.

    摘要翻译: 用于基于微控制器的闪存数字控制器系统的命令解码器包括多个子系统,包括命令解码器,其用作解释来自用户的命令的主用户界面,并管理命令和命令模式的优先级。 命令解码器还存储关键信息,包括由包括程序缓冲器,突发读取模块,寄存器块和微控制器的其他子系统使用的地址,数据,操作码和各种标志寄存器。 此外,命令解码器包含时钟同步逻辑,控制微控制器的睡眠功能,并作为测试模式控制器。

    Method and apparatus for determining the background of an image sequence
    8.
    发明授权
    Method and apparatus for determining the background of an image sequence 有权
    用于确定图像序列的背景的方法和装置

    公开(公告)号:US07574038B1

    公开(公告)日:2009-08-11

    申请号:US11096998

    申请日:2005-03-31

    IPC分类号: G06K9/00 G06K9/20

    CPC分类号: G06T7/215 G06T2207/10016

    摘要: One embodiment of the present invention provides a system that determines a background image for a sequence of image frames. During operation, the system receives a sequence of input image-frames, wherein an input image-frame associates pixels with pixel-attributes. The system then computes a labeling, wherein the labeling associates pixels in the output background image with input image-frames in the sequence of input image-frames. Next, the system determines the output background image using the sequence of input image-frames and the labeling.

    摘要翻译: 本发明的一个实施例提供一种确定图像帧序列的背景图像的系统。 在操作期间,系统接收输入图像帧的序列,其中输入图像帧将像素与像素属性相关联。 然后,系统计算标签,其中标签将输出背景图像中的像素与输入图像帧序列中的输入图像帧相关联。 接下来,系统使用输入图像帧和标签的顺序来确定输出背景图像。

    VALUE ADDED BUSINESS MONITORING AND REPORTING SYSTEMS AND METHODS
    9.
    发明申请
    VALUE ADDED BUSINESS MONITORING AND REPORTING SYSTEMS AND METHODS 审中-公开
    增值业务监控和报告系统和方法

    公开(公告)号:US20090070169A1

    公开(公告)日:2009-03-12

    申请号:US12197011

    申请日:2008-08-22

    申请人: Scott Cohen

    发明人: Scott Cohen

    IPC分类号: G06Q10/00 G06Q40/00

    摘要: Systems, method and reports, for executing calculating economic and tax capital balances at the partner/shareholder level for partnerships and unitized companies are disclosed. The system provides full reporting and allows for business information to be transmitted electronically and in multiple formats. The system also allows a user to retrieve a business entity's foundation documents within the system.

    摘要翻译: 披露了合伙人/股东级别合伙企业和单位化公司执行计算经济和税收资本余额的制度,方法和报告。 该系统提供完整的报告,并允许以电子方式和多种格式传输业务信息。 该系统还允许用户在系统内检索业务实体的基础文档。