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    TECHNOLOGIES FOR ACCESS CONTROL
    3.
    发明申请
    TECHNOLOGIES FOR ACCESS CONTROL 有权
    技术获取控制

    公开(公告)号：US20160191530A1

    公开(公告)日：2016-06-30

    申请号：US14583638

    申请日：2014-12-27

    Applicant: Sanjeev Jain ,  Ronen Chayat

    Inventor： Sanjeev Jain ,  Ronen Chayat

    IPC: H04L29/06

    CPC classification number: H04L63/101 ,  H04L45/74 ,  H04L63/20 ,  H04L69/22

    Abstract: Technologies for performing access control include a computing device that parses a network packet received by the computing device to identify an n-tuple of a header of the network packet, wherein the n-tuple is associated with one or more access control rules. The computing devices determines a bitmask associated with an access control rule of a virtual machine of the computing device and applies the determined bitmask to the n-tuple of the network packet to generate a masked n-tuple. Further, the computing device generates a hash of the masked n-tuple and compares the generated hash to a reference hash associated with the access control rule to identify a match. The computing device performs an access control action in response to identifying a match between the generated hash and the reference hash.

    Abstract translation: 用于执行访问控制的技术包括计算设备，其解析由所述计算设备接收的网络分组以识别所述网络分组的报头的n元组，​​其中所述n元组与一个或多个访问控制规则相关联。 计算设备确定与计算设备的虚拟机的访问控制规则相关联的位掩码，并将确定的位掩码应用于网络分组的n元组以生成被掩蔽的n元组。 此外，计算设备生成掩蔽的n元组的散列，并将生成的散列与与访问控制规则相关联的引用散列进行比较，以识别匹配。 响应于识别生成的散列和引用散列之间的匹配，计算设备执行访问控制动作。

    Method and apparatus for scheduling packets
    4.
    发明授权
    Method and apparatus for scheduling packets 失效
    调度数据包的方法和装置

    公开(公告)号：US07522620B2

    公开(公告)日：2009-04-21

    申请号：US10640206

    申请日：2003-08-12

    Applicant: John Wishneusky ,  Sanjeev Jain ,  David Romano

    Inventor： John Wishneusky ,  Sanjeev Jain ,  David Romano

    IPC: H04L12/56

    CPC classification number: H04L47/6215 ,  H04L47/50 ,  H04L47/527 ,  H04L47/6225

    Abstract: A method and apparatus for scheduling packets using a pre-sort deficit round-robin method. Scheduling decisions for packets are made when packets are received, and entries for the received packets are stored in a pre-sorted scheduling array. A packet is transmitted by dequeuing the packet from the pre-sorted scheduling array.

    Abstract translation: 一种使用预排序缺陷循环方法来调度分组的方法和装置。 当分组被接收时进行分组的调度决定，并且接收的分组的条目存储在预先排序的调度数组中。 通过从预先排序的调度数组中排队数据包来发送数据包。

    Processor having content addressable memory for block-based queue structures
    5.
    发明授权
    Processor having content addressable memory for block-based queue structures 有权
    具有内容可寻址存储器的处理器，用于基于块的队列结构

    公开(公告)号：US07467256B2

    公开(公告)日：2008-12-16

    申请号：US11027601

    申请日：2004-12-28

    Applicant: Sanjeev Jain ,  Gilbert M. Wolrich ,  Debra Bernstein

    Inventor： Sanjeev Jain ,  Gilbert M. Wolrich ,  Debra Bernstein

    IPC: G06F12/00

    CPC classification number: H04L49/901 ,  H04L45/7453 ,  H04L49/90

    Abstract: Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.

    Abstract translation: 排队命令信息存储在内容可寻址存储器（CAM）中，其中接收到用于第一队列的排队命令，检查CAM以确定是否存在用于第一队列的命令，并且如果发现第一队列的命令是 在多个CAM条目中，信息被存储在所接收的命令的链表中。

    Enqueueing entries in a packet queue referencing packets
    8.
    发明授权
    Enqueueing entries in a packet queue referencing packets 有权
    引用数据包的数据包队列中的入队条目

    公开(公告)号：US07366865B2

    公开(公告)日：2008-04-29

    申请号：US10936917

    申请日：2004-09-08

    Applicant: Sridhar Lakshmanamurthy ,  Sanjeev Jain ,  Gilbert Wolrich ,  Debra Bernstein

    Inventor： Sridhar Lakshmanamurthy ,  Sanjeev Jain ,  Gilbert Wolrich ,  Debra Bernstein

    IPC: G06F12/06 ,  H04N7/16

    CPC classification number: G06F12/0804 ,  G06F12/0875

    Abstract: Provided are a method, system, network processor, network device, and article of manufacture for enqueueing entries in a packet queue referencing packets. When adding a packet to a first memory area, an entry is written to a packet queue in a second memory area referencing the added packet. A pointer is read referencing one end of the packet queue from a queue descriptor in the second memory area into a third memory area in one read operation. The pointer is updated in the third memory area to point to the added entry in the packet queue and the updated pointer in the third memory area is written to the queue descriptor in the second memory area in one write operation.

    Abstract translation: 提供了一种方法，系统，网络处理器，网络设备和用于引入分组的分组队列中的入口的入口制品。 当向第一存储器区域添加分组时，将条目写入参考所添加的分组的第二存储器区域中的分组队列。 在一次读取操作中，将指针从第二存储器区域中的队列描述符引用到分组队列的一端到第三存储器区域中。 指针在第三存储器区域被更新以指向分组队列中的添加的条目，并且在一个写入操作中将第三存储器区域中的更新的指针写入第二存储器区域中的队列描述符。

    Program memory having flexible data storage capabilities
    9.
    发明申请
    Program memory having flexible data storage capabilities 审中-公开
    具有灵活数据存储功能的程序存储器

    公开(公告)号：US20080022175A1

    公开(公告)日：2008-01-24

    申请号：US11478393

    申请日：2006-06-29

    Applicant: Sanjeev Jain ,  Mark B. Rosenbluth ,  Gilbert M. Wolrich ,  Jose S. Niell

    Inventor： Sanjeev Jain ,  Mark B. Rosenbluth ,  Gilbert M. Wolrich ,  Jose S. Niell

    IPC: G01R31/28

    CPC classification number: G06F9/3802 ,  G06F9/30043 ,  G06F9/342 ,  G06F9/3824 ,  G06F9/3851

    Abstract: A method according to one embodiment may include performing one or more fetch operations to retrieve one or more instructions from a program memory; scheduling a write instruction to write data from at least one data register into the program memory; and stealing one or more cycles from one or more of the fetch operations to write the data in the at least one data register into the program memory. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

    Abstract translation: 根据一个实施例的方法可以包括执行一个或多个提取操作以从程序存储器检索一个或多个指令; 调度写指令以将数据从至少一个数据寄存器写入程序存储器; 以及从一个或多个获取操作中窃取一个或多个周期，以将所述至少一个数据寄存器中的数据写入程序存储器。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

    Buffer circuit
    10.
    发明申请
    Buffer circuit 审中-公开
    缓冲电路

    公开(公告)号：US20070052443A1

    公开(公告)日：2007-03-08

    申请号：US10556005

    申请日：2004-05-07

    Applicant: Atul Katoch ,  Sanjeev Jain ,  Rinze Meijer

    Inventor： Atul Katoch ,  Sanjeev Jain ,  Rinze Meijer

    IPC: H03K19/003

    CPC classification number: H03K19/00361 ,  H03K19/0027

    Abstract: A buffer circuit (31), for example a repeater or receiver circuit for a signal wire of an on-chip bus, receives an input signal, and produces an output signal. The buffer circuit (31) comprises a first inverting stage (7) and a second inverter stage (9). The second inverting stage (9) provides the drive for the output (5). The first inverting stage (7) has additional circuitry (15, 17, 19, 21, 23, 25, 27, 29) for controlling the strengths of the pull up path and the pull down path. The pull up/down paths are dynamically controlled according to the status of one or more aggressor signals. In one embodiment the switching threshold is lowered only in the worst case delay scenario, i.e. when the signal wire (3) is at a different logic level to the aggressor signals. In another embodiment, the switching threshold is raised when the signal wire and aggressor signals are all at the same logic level, thereby reducing crosstalk.

    Abstract translation: 缓冲电路（31），例如用于片上总线的信号线的中继器或接收器电路，接收输入信号，并产生输出信号。 缓冲电路（31）包括第一反相级（7）和第二反相器级（9）。 第二反相级（9）为输出（5）提供驱动。 第一反相级（7）具有用于控制上拉路径和下拉路径的强度的附加电路（15,17,19,21,23,25,27,29）。 根据一个或多个攻击者信号的状态来动态地控制上拉/下拉路径。 在一个实施例中，切换阈值仅在最坏情况下延迟情况下降低，即当信号线（3）与侵略者信号处于不同的逻辑电平时。 在另一个实施例中，当信号线和侵扰器信号都处于相同的逻辑电平时，切换阈值升高，从而减少串扰。

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