公开(公告)号：US09286160B2

公开(公告)日：2016-03-15

申请号：US14175843

申请日：2014-02-07

Applicant: STMicroelectronics International NV ,  STMicroelectronics S.r.l.

Inventor： BharathManoj Manda ,  Abhishek Lal ,  Marco Pasotti ,  Marcella Carissimi

IPC: G11C11/00 ,  G06F11/10 ,  G11C13/00

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2029/0411 ,  G11C2211/5646

Abstract: According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.

Abstract translation: 根据实施例，相变存储器（PCM）阵列包括分组成存储块的多个存储器单元。 在PCM阵列中，每个存储单元是PCM单元。 PCM阵列还包括多个擦除标志单元。 多个擦除标志单元的每个擦除标志单元与存储块相关联，并且指示存储器块是否存储有效数据或擦除的数据。

公开(公告)号：US20150228338A1

公开(公告)日：2015-08-13

申请号：US14175843

申请日：2014-02-07

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics International NV

Inventor： BharathManoj Manda ,  Abhishek Lal ,  Marco Pasotti ,  Marcella Carissimi

IPC: G11C13/00 ,  G06F11/10

CPC classification number: G06F11/1076 ,  G06F11/1048 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2029/0411 ,  G11C2211/5646

Abstract: According to embodiments, a phase change memory (PCM) array includes a plurality of memory cells grouped into memory blocks. In the PCM array, each memory cell is a PCM cell. The PCM array also includes a plurality of erase flag cells. Each erase flag cell of the plurality of erase flag cells is associated with a memory block and indicates whether the memory block stores valid data or erased data.

Abstract translation: 根据实施例，相变存储器（PCM）阵列包括分组成存储块的多个存储器单元。 在PCM阵列中，每个存储单元是PCM单元。 PCM阵列还包括多个擦除标志单元。 多个擦除标志单元的每个擦除标志单元与存储块相关联，并且指示存储器块是否存储有效数据或擦除的数据。

公开(公告)号：US20130328150A1

公开(公告)日：2013-12-12

申请号：US13895715

申请日：2013-05-16

Applicant: STMicroelectronics International NV

Inventor： Raul Andres BIANCHI ,  Pascal FONTENEAU

IPC: H01L31/0256 ,  H01L27/144 ,  H01L31/18

CPC classification number: H01L31/0256 ,  H01L27/144 ,  H01L29/0684 ,  H01L29/66113 ,  H01L29/866 ,  H01L31/1892

Abstract: An avalance diode including, between two heavily-doped regions of opposite conductivity types arranged at the surface of a semiconductor region, a lightly-doped region, with length L of the lightly-doped region between the heavily-doped regions approximately ranging between 50 and 200 nm.

Abstract translation: 一种平均二极管，包括布置在半导体区域的表面处的相反导电类型的两个重掺杂区域之间的轻掺杂区域，重掺杂区域之间的轻掺杂区域的长度L大约在50和 200nm。

公开(公告)号：US08570085B2

公开(公告)日：2013-10-29

申请号：US13689476

申请日：2012-11-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International NV

Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Pankaj Rohilla

IPC: H03K3/289 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本公开涉及一种具有数据保持功能的低功耗触发器电路，包括至少一个触发器和连接到触发器的输出的至少一个保持单元，并配置为使得在触发器的正常操作期间 电路中，保持单元将触发器的输出端子上存在的数据或逻辑状态发送到其自己的输出端子，而在触发器电路的低功耗操作期间，保持单元的锁存电路适合于存储数据或 激活与触发器的输出端子上存在的最后数据或逻辑状态对应的逻辑状态。

公开(公告)号：US20130088272A1

公开(公告)日：2013-04-11

申请号：US13689476

申请日：2012-11-29

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International NV

Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Pankaj Rohilla

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/0375 ,  H03K3/356008 ,  H03K19/0016

Abstract: The present disclosure relates to a low consumption flip-flop circuit with data retention, comprising at least one flip-flop and at least one retention cell connected to the output of the flip-flop and configured so that during normal operation of the flip-flop circuit, the retention cell transmits the data or logic state present on the output terminal of the flip-flop to its own output terminal, while during low consumption operation of the flip-flop circuit a latch circuit of the retention cell suitable to memorize data or a logic state corresponding to the last data or logic state present on the output terminal of the flip-flop is activated.

Abstract translation: 本公开涉及一种具有数据保持功能的低功耗触发器电路，包括至少一个触发器和连接到触发器的输出的至少一个保持单元，并配置为使得在触发器的正常操作期间 电路中，保持单元将触发器的输出端子上存在的数据或逻辑状态发送到其自己的输出端子，而在触发器电路的低功耗操作期间，保持单元的锁存电路适合于存储数据或 激活与触发器的输出端子上存在的最后数据或逻辑状态对应的逻辑状态。

公开(公告)号：US11209482B1

公开(公告)日：2021-12-28

申请号：US17107370

申请日：2020-11-30

Applicant: STMicroelectronics International NV

Inventor： Vivek Mohan Sharma ,  Deepak Baranwal ,  Amulya Pandey

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3193 ,  G06F11/22

Abstract: A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.