公开(公告)号：US11209482B1

公开(公告)日：2021-12-28

申请号：US17107370

申请日：2020-11-30

Applicant: STMicroelectronics International NV

Inventor： Vivek Mohan Sharma ,  Deepak Baranwal ,  Amulya Pandey

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3193 ,  G06F11/22

Abstract: A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.