公开(公告)号：US06728890B1

公开(公告)日：2004-04-27

申请号：US09670417

申请日：2000-09-26

申请人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

发明人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC分类号： G06R126

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126

摘要： A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.

摘要翻译： 提供一种用于控制总线和与其耦合的部件的操作的方法。 该方法包括从耦合到总线的组件中的一个接收对总线事务的请求。 此后，提供给至少请求组件的时钟信号的频率增加，并且对所请求的总线事务进行维修。 在请求的总线事务完成时，提供给至少请求组件的时钟信号的频率降低。

公开(公告)号：US06691215B1

公开(公告)日：2004-02-10

申请号：US09670418

申请日：2000-09-26

申请人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

发明人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC分类号： G06F1200

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

摘要： A memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.

摘要翻译： 提供了一种存储系统。 存储器系统包括存储器，时钟信号发生器，锁相环电路和旁路电路。 时钟信号发生器产生第一时钟信号。 时钟信号发生器具有第一工作模式，其中第一时钟信号具有第一频率和第二工作模式，其中第一时钟信号具有第二频率。 锁相环电路与存储器相关联，并且适于接收第一时钟信号并向存储器提供同步的第二时钟信号。 旁路电路适于在第二操作模式中将第一时钟信号传送到存储器。

公开(公告)号：US08970571B1

公开(公告)日：2015-03-03

申请号：US13419299

申请日：2012-03-13

申请人： Adrian Wong ,  Russell N. Mirov

发明人： Adrian Wong ,  Russell N. Mirov

IPC分类号： G09G5/00

CPC分类号： G02B27/0172 ,  G02B27/0101 ,  G02B27/283 ,  G02B2027/0112 ,  G02B2027/0118 ,  G02B2027/014 ,  G02B2027/0178 ,  G02B2027/0194 ,  G02F1/133621 ,  G09G3/3406 ,  G09G3/3413 ,  G09G2320/0626 ,  G09G2320/064 ,  G09G2320/0666 ,  G09G2360/144 ,  G09G2360/145

摘要： An apparatus includes a light source, a display array, a light relay, a photodetector, control circuitry, and measurement circuitry. The light source is for providing lamp light during an ON-time of the light source. The display array is positioned to receive and selectively manipulate the lamp light. The light relay is positioned to receive the image light from the display array. The photodetector is optically coupled to receive light. Control circuitry is coupled to the light source for cycling the light source and coupled to the measurement circuitry for coordinating light measurements of the photodetector.

摘要翻译： 一种装置包括光源，显示阵列，光继电器，光电检测器，控制电路和测量电路。 光源用于在光源的接通时间期间提供灯光。 显示阵列被定位成接收和选择性地操纵灯光。 光继电器被定位成从显示器阵列接收图像光。 光电检测器被光耦合以接收光。 控制电路耦合到光源，用于循环光源并耦合到测量电路，用于协调光电检测器的光测量。

公开(公告)号：US07514937B2

公开(公告)日：2009-04-07

申请号：US11284354

申请日：2005-11-21

申请人： Russell N. Mirov ,  Howard L. Davidson

发明人： Russell N. Mirov ,  Howard L. Davidson

IPC分类号： G01R31/04 ,  G01R31/08

CPC分类号： G01R31/312 ,  G01R31/046 ,  G01R31/2812 ,  G01R31/2853

摘要： A system configured to detect faults in signal lines. A system includes a first component configured to communicate with a second component via a signal path including one or more signal traces. Sense signal lines are manufactured such that at some point they are in close proximity to a signal trace which is to be monitored. The sense signal lines are configured to use parasitic coupling to redirect a portion of a signal conveyed via a signal trace to a monitoring component. The first component is configured to convey a test signal indicative of a type of test via the signal path, and a reference signal to the monitoring component. The monitoring component is configured to utilize the reference signal to ascertain a presence or absence, or characteristics of a received redirected signal. The monitoring component may optionally utilize a locally generated reference signal.

摘要翻译： 被配置为检测信号线路中的故障的系统。 系统包括被配置为经由包括一个或多个信号迹线的信号路径与第二部件通信的第一部件。 感测信号线被制造成使得在某些点处它们处于要被监控的信号迹线附近。 感测信号线被配置为使用寄生耦合来将经由信号迹线传送的信号的一部分重定向到监视部件。 第一组件被配置为经由信号路径传送指示测试类型的测试信号，以及向监视组件传送参考信号。 监视组件被配置为利用参考信号来确定所接收的重定向信号的存在或不存在或特性。 监视组件可以可选地利用本地生成的参考信号。

公开(公告)号：US06836824B1

公开(公告)日：2004-12-28

申请号：US09670368

申请日：2000-09-26

申请人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

发明人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC分类号： G06F1200

CPC分类号： G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

摘要： A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.

摘要翻译： 提供了一种用于操作具有休眠模式的高速缓存的方法。 高速缓存位于计算机系统的存储器层次结构中，并且该方法包括接收第一高速缓存请求并且服务于第一高速缓存请求。 响应于完成第一高速缓存请求的服务而断言睡眠模式信号。 此后，接收到第二高速缓存请求，并且响应于接收到第二高速缓存请求，休眠模式信号被断言。 此后，服务第二高速缓存请求。

公开(公告)号：US06748546B1

公开(公告)日：2004-06-08

申请号：US09670041

申请日：2000-09-26

申请人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

发明人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC分类号： G06F126

CPC分类号： G06F1/206 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16

摘要： A method for controlling thermal cycles in a computer system is provided. The method is comprised of receiving a request to transition the computer system from a first operating mode to a second operating mode, where less power is consumed in the second operating mode. A historical rate at which the computer system has transitioned between the first and second operating modes is determined, and the requested transition is permitted in response to the historical rate being less than a first preselected setpoint, but denied in response to the historical rate being greater than the first preselected setpoint.

摘要翻译： 提供了一种用于控制计算机系统中的热循环的方法。 该方法包括接收将计算机系统从第一操作模式转换到第二操作模式的请求，其中在第二操作模式中消耗较少的功率。 确定计算机系统在第一和第二操作模式之间转换的历史速率，并且响应于历史速率小于第一预选设定值而允许所请求的转换，但是响应于历史速率更大而拒绝 比第一个预选设定值。

公开(公告)号：US06528974B1

公开(公告)日：2003-03-04

申请号：US09669357

申请日：2000-09-26

申请人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

发明人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC分类号： G05F1577

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

摘要： A power supply is provided. The power supply is comprised of a first power module, a second power module, and a controller. The first power module is capable of delivering a first preselected amount of power. The second power module is capable of delivering a second preselected amount of power. The first and second power modules are coupled together to be capable of delivering an aggregate amount of power related to the first and second preselected amounts of power. The controller is adapted to selectively enable the first and second power modules to make power available in one of the first preselected amount, the second preselected amount, and the aggregate amount.

摘要翻译： 提供电源。 电源由第一电源模块，第二电源模块和控制器组成。 第一电源模块能够提供第一预选量的电力。 第二电源模块能够传递第二预选量的电力。 第一和第二功率模块耦合在一起，以能够传递与第一和第二预选量的功率有关的总量的功率。 控制器适于选择性地使得第一和第二功率模块能够以第一预选量，第二预选量和总量中的一种来供电。

公开(公告)号：US5790890A

公开(公告)日：1998-08-04

申请号：US608745

申请日：1996-02-29

申请人： Russell N. Mirov ,  Victor Odisho

发明人： Russell N. Mirov ,  Victor Odisho

IPC分类号： G06F13/14 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06F17/00

CPC分类号： G06F11/2289 ,  G06F12/0684 ,  G06F15/177 ,  G06F9/4411

摘要： An identification interface that transfers control information between a controller and an option module coupled to a motherboard of a computer. The identification interface supports the propagation of a plurality of bit fields containing information pertaining to the characteristics of the option module including, but not limited to, its speed, type and other information about its characteristics.

摘要翻译： 在控制器和耦合到计算机的主板的选件模块之间传送控制信息的识别接口。 识别接口支持包含与选项模块的特性有关的信息的多个位域的传播，包括但不限于其速度，类型和关于其特性的其它信息。

公开(公告)号：US06700421B1

公开(公告)日：2004-03-02

申请号：US09669825

申请日：2000-09-26

申请人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

发明人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC分类号： H03L706

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

摘要： A phase locked loop circuit is provided. The phase locked loop circuit is comprised of a first and second divide-by-N counter, a phase comparator, a voltage controlled oscillator, a clock tree, and a feedback path. The first divide-by-N counter is adapted to receive a first clock signal and provide a second clock signal. The phase comparator has a first and second input terminal and an output terminal. The phase comparator is adapted to compare the phase of signals applied to the first and second input terminals and deliver a signal at the output terminal having a magnitude indicative of a difference in the phases of the signals. The first input terminal is coupled to receive the second clock signal. The voltage controlled oscillator is coupled to receive the phase difference signal and deliver a third clock signal having a frequency responsive thereto. The second divide-by-N counter is coupled to receive the third clock signal and deliver a fourth clock signal. The clock tree is coupled to receive the third clock signal and deliver at least one fourth clock signal. The feedback path is coupled to deliver the fourth clock signal to the second input terminal of the phase comparator.

摘要翻译： 提供了一个锁相环电路。 锁相环电路由第一和第二除N计数器，相位比较器，压控振荡器，时钟树和反馈路径组成。 第一分频计数器适于接收第一时钟信号并提供第二时钟信号。 相位比较器具有第一和第二输入端子和输出端子。 相位比较器适于比较施加到第一和第二输入端的信号的相位，并在输出端递送具有表示信号相位差的幅度的信号。 第一输入端耦合以接收第二时钟信号。 电压控制振荡器被耦合以接收相位差信号并传送具有对其响应的频率的第三时钟信号。 第二分频计数器被耦合以接收第三时钟信号并传送第四时钟信号。 时钟树被耦合以接收第三时钟信号并且递送至少一个第四时钟信号。 反馈路径被耦合以将第四时钟信号传送到相位比较器的第二输入端。

公开(公告)号：US06608476B1

公开(公告)日：2003-08-19

申请号：US09670143

申请日：2000-09-26

申请人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

发明人： Russell N. Mirov ,  Michel Cekleov ,  Mark Young ,  William M. Baldwin

IPC分类号： G01R1132

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

摘要： A method is provided for operating an electronic device by monitoring operating characteristics of the electronic device, and determining from the monitored operating characteristics to operate at least a portion of components within the electronic device in a first, second, or third mode of operation. The first, second, and third modes of operation consume power at first, second, and third different rates. At least a portion of the components are instructed to switch between the first, second, and third modes.

摘要翻译： 提供一种用于通过监视电子设备的操作特性来操作电子设备的方法，以及根据所监视的操作特性来确定在第一，第二或第三操作模式下操作电子设备内的部件的至少一部分。 第一，第二和第三种操作模式以第一，第二和第三种不同的速率消耗功率。 指示部件的至少一部分在第一，第二和第三模式之间切换。