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公开(公告)号：US5031146A
公开(公告)日：1991-07-09
申请号：US288168
申请日：1988-12-22
IPC分类号： G06F12/08 , G06F12/00 , G06F13/38 , G06F15/16 , G06F15/177 , G11C11/00 , G11C11/413
CPC分类号： G11C11/005
摘要： Memory apparatus for simultaneously transferring data between corresponding memory cells of two RAMs is disclosed. The two memories are fabricated on a common integrated circuit chip substrate with the corresponding memory cells of the two memories positioned adjacent one another and interconnected through a pair of transfer transistors. The transfer transistors as well as the power supply to each memory cell are controllable to cause the simultaneous copying of the data from the cells of one RAM into the corresponding cells of the other RAM.
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公开(公告)号：US3962589A
公开(公告)日：1976-06-08
申请号：US548189
申请日：1975-02-10
申请人： Ury Priel , Robert A. Anselmo
发明人： Ury Priel , Robert A. Anselmo
IPC分类号： H03K19/088 , H03K19/40
CPC分类号： H03K19/088
摘要： A dual inverter circuit wherein the first inverter circuit includes a pair of phase splitter transistors, one serving to feed the base of the pull-up transistor in the first inverter circuit and the other serving to feed the base of the phase splitter transistor in the second inverter circuit. The circuit provides a minimum delay time between the operation of the first inverter and the turn-on time of the second inverter while also providing active pull-up circuits, i.e., pull-up transistors, in the two inverters to insure fast operate times for both inverters especially desirable when feeding into large capacitance loads.
摘要翻译： 一种双反相器电路，其中第一反相器电路包括一对分相晶体管，一对用于馈送第一反相器电路中的上拉晶体管的基极，另一个用于在第二反相器晶体管的基极中馈送第二 逆变电路。 该电路在第一反相器的操作和第二反相器的导通时间之间提供最小延迟时间，同时在两个反相器中还提供有源上拉电路，即上拉晶体管，以确保快速操作时间 当馈入大电容负载时，两个逆变器特别理想。
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公开(公告)号：US07619539B2
公开(公告)日：2009-11-17
申请号：US10824248
申请日：2004-04-14
IPC分类号： G05B19/02
CPC分类号： H05B41/36 , H05B37/0254 , H05B37/0272
摘要： A ballast having a microprocessor embedded therein is controlled via four inputs. The ballast includes a high-voltage phase-controlled signal provided by a dimmer and an infrared (IR) receiver through which the ballast can receive data signals from an IR transmitter. The ballast can also receive commands from other ballasts or a master control on the serial digital communication link, such as a DALI protocol link. The fourth input is an analog signal, which is simply a DC signal that linearly ranges in value from a predetermined lower limit to a predetermined upper limit, corresponding to the 0% to 100% dimming range of the load. The output stage of the ballast includes one or more FETs, which are used to control the current flow to the lamp. Based on these inputs, the microprocessor makes a decision on the intensity levels of the load and directly drives the FETs in the output stage.
摘要翻译： 其中嵌有微处理器的镇流器通过四个输入进行控制。 镇流器包括由调光器和红外（IR）接收器提供的高压相位控制信号，镇流器可以通过该接收器从IR发射器接收数据信号。 镇流器还可以从串行数字通信链路（例如DALI协议链路）接收来自其他镇流器的命令或主控制器。 第四输入是模拟信号，其仅仅是对应于负载的0％至100％调光范围的从预定下限到预定上限的线性范围的直流信号。 镇流器的输出级包括一个或多个FET，用于控制流向灯的电流。 基于这些输入，微处理器对负载的强度水平做出决定，并直接驱动输出级的FET。
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公开(公告)号：US20090273296A1
公开(公告)日：2009-11-05
申请号：US12503559
申请日：2009-07-15
IPC分类号： H05B41/36
CPC分类号： H05B41/36 , H05B37/0254 , H05B37/0272
摘要： A ballast having a microprocessor embedded therein is controlled via four inputs. The ballast includes a high-voltage phase-controlled signal provided by a dimmer and an infrared (IR) receiver through which the ballast can receive data signals from an IR transmitter. The ballast can also receive commands from other ballasts or a master control on the serial digital communication link, such as a DALI protocol link. The fourth input is an analog signal, which is simply a DC signal that linearly ranges in value from a predetermined lower limit to a predetermined upper limit, corresponding to the 0% to 100% dimming range of the load. The output stage of the ballast includes one or more FETs, which are used to control the current flow to the lamp. Based on these inputs, the microprocessor makes a decision on the intensity levels of the load and directly drives the FETs in the output stage.
摘要翻译： 其中嵌有微处理器的镇流器通过四个输入进行控制。 镇流器包括由调光器和红外（IR）接收器提供的高压相位控制信号，镇流器可以通过该接收器从IR发射器接收数据信号。 镇流器还可以从串行数字通信链路（例如DALI协议链路）接收来自其他镇流器的命令或主控制器。 第四输入是模拟信号，其仅仅是对应于负载的0％至100％调光范围的从预定下限到预定上限的线性范围的直流信号。 镇流器的输出级包括一个或多个FET，用于控制流向灯的电流。 基于这些输入，微处理器对负载的强度水平做出决定，并直接驱动输出级的FET。
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公开(公告)号：US20090273286A1
公开(公告)日：2009-11-05
申请号：US12503588
申请日：2009-07-15
IPC分类号： H05B41/36
CPC分类号： H05B41/36 , H05B37/0254 , H05B37/0272
摘要： A ballast having a microprocessor embedded therein is controlled via four inputs. The ballast includes a high-voltage phase-controlled signal provided by a dimmer and an infrared (IR) receiver through which the ballast can receive data signals from an IR transmitter. The ballast can also receive commands from other ballasts or a master control on the serial digital communication link, such as a DALI protocol link. The fourth input is an analog signal, which is simply a DC signal that linearly ranges in value from a predetermined lower limit to a predetermined upper limit, corresponding to the 0% to 100% dimming range of the load. The output stage of the ballast includes one or more FETs, which are used to control the current flow to the lamp. Based on these inputs, the microprocessor makes a decision on the intensity levels of the load and directly drives the FETs in the output stage.
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6.发明授权Digital processing system including plural memory devices and data transfer circuitry 失效数字处理系统包括多个存储器件和数据传输电路
公开(公告)号：US5287485A
公开(公告)日：1994-02-15
申请号：US41129
申请日：1993-03-31
IPC分类号： G11C11/00 , G06F13/00 , G11C11/413
CPC分类号： G11C11/005
摘要： A digital processing system includes first and second processors and first and second random access memories (RAMs) respectively associated with the first and second processors. Each of the first and second RAMs includes a plurality of independent memory cells, each cell in the first RAM having associated therewith a corresponding cell in the second RAM. Input/output circuitry provides independent access by the first processor to the first RAM and by the second processor to the second RAM. Control logic is responsive to a transfer control signal to simultaneously transfer data stored in the memory cells of one of the first and second RAMs into the corresponding cells of the other of the first and second RAMs. Data may be selectively transferred such that only data stored in selected memory cells is transferred between the first and second RAMs.
摘要翻译： 数字处理系统包括分别与第一和第二处理器相关联的第一和第二处理器以及第一和第二随机存取存储器（RAM）。 第一和第二RAM中的每一个包括多个独立存储器单元，第一RAM中的每个单元与第二RAM中的相应单元相关联。 输入/输出电路提供第一处理器对第一RAM和第二处理器对第二RAM的独立访问。 控制逻辑响应于传送控制信号，以将存储在第一和第二RAM中的一个的存储单元中的数据同时传送到第一和第二RAM中另一个的相应单元。 可以选择性地传送数据，使得仅存储在所选择的存储器单元中的数据在第一和第二RAM之间传送。
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公开(公告)号：US5193071A
公开(公告)日：1993-03-09
申请号：US844883
申请日：1992-03-03
IPC分类号： G11C11/00
CPC分类号： G11C11/005
摘要： Memory apparatus for simultaneously transferring data between corresponding memory cells of two RAMs is disclosed. The two memories are fabricated on a common integrated circuit chip substrate with the corresponding memory cells of the two memories positioned adjacent one another and interconnected through a pair of transfer transistors. The transfer transistors as well as the power supply to each memory cell are controllable to cause the simultaneous copying of the data from the cells of one RAM into the corresponding cells of the other RAM.
摘要翻译： 公开了用于在两个RAM的相应存储单元之间同时传送数据的存储装置。 这两个存储器在公共集成电路芯片基板上制造，其中两个存储器的对应存储器单元彼此相邻定位并通过一对转移晶体管互连。 转移晶体管以及向每个存储单元的电源是可控制的，以便将数据从一个RAM的单元同时复制到另一个RAM的相应单元中。
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公开(公告)号：US08111008B2
公开(公告)日：2012-02-07
申请号：US12503559
申请日：2009-07-15
IPC分类号： G05F1/00
CPC分类号： H05B41/36 , H05B37/0254 , H05B37/0272
摘要： A ballast having a microprocessor embedded therein is controlled via four inputs. The ballast includes a high-voltage phase-controlled signal provided by a dimmer and an infrared (IR) receiver through which the ballast can receive data signals from an IR transmitter. The ballast can also receive commands from other ballasts or a master control on the serial digital communication link, such as a DALI protocol link. The fourth input is an analog signal, which is simply a DC signal that linearly ranges in value from a predetermined lower limit to a predetermined upper limit, corresponding to the 0% to 100% dimming range of the load. The output stage of the ballast includes one or more FETs, which are used to control the current flow to the lamp. Based on these inputs, the microprocessor makes a decision on the intensity levels of the load and directly drives the FETs in the output stage.
摘要翻译： 其中嵌有微处理器的镇流器通过四个输入进行控制。 镇流器包括由调光器和红外（IR）接收器提供的高压相位控制信号，镇流器可以通过该接收器从IR发射器接收数据信号。 镇流器还可以从串行数字通信链路（例如DALI协议链路）接收来自其他镇流器的命令或主控制器。 第四输入是模拟信号，其仅仅是对应于负载的0％至100％调光范围的从预定下限到预定上限的线性范围的直流信号。 镇流器的输出级包括一个或多个FET，用于控制流向灯的电流。 基于这些输入，微处理器对负载的强度水平做出决定，并直接驱动输出级的FET。
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