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公开(公告)号：US20150242210A1
公开(公告)日：2015-08-27
申请号：US14190404
申请日：2014-02-26
CPC分类号： G06F9/30036 , G06F9/30189 , G06F9/3887 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F2201/81 , G06F2201/88 , Y02D10/34
摘要： In an embodiment, a processor includes a vector execution unit having a plurality of lanes to execute operations on vector operands, a performance monitor coupled to the vector execution unit to maintain information regarding an activity level of the lanes, and a control logic coupled to the performance monitor to control power consumption of the vector execution unit based at least in part on the activity level of at least some of the lanes. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，处理器包括具有多个通道以执行向量操作数的操作的向量执行单元，耦合到向量执行单元的性能监视器，以维护关于通道的活动级别的信息，以及耦合到该通道的控制逻辑 性能监视器，用于至少部分地基于至少一些车道的活动水平来控制向量执行单元的功率消耗。 描述和要求保护其他实施例。
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公开(公告)号：US20140379998A1
公开(公告)日：2014-12-25
申请号：US13922072
申请日：2013-06-19
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813 , G06F12/0817 , G06F2212/621 , Y02D10/13
摘要： Technologies for dynamic home tile mapping are described. an address request can be received from a processing core, the processing core being associated with a home tile table, the home tile table including respective mappings of one or more directory addresses to one or more home tiles. A buffer can be scanned to identify a presence of the address within the buffer. Based on an identification of the presence of the address within the buffer, a home tile identifier corresponding to the address can be provided from the buffer.
摘要翻译： 描述了用于动态家庭瓦片映射的技术。 可以从处理核心接收地址请求，处理核心与家庭瓦片表相关联，家庭瓦片表包括一个或多个目录地址到一个或多个家庭瓦片的各自的映射。 可以扫描缓冲区以识别缓冲区内存在的地址。 基于缓冲器中地址的存在的识别，可以从缓冲器提供对应于地址的归属瓦片标识符。
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公开(公告)号：US09244746B2
公开(公告)日：2016-01-26
申请号：US13956609
申请日：2013-08-01
摘要： A processing device comprises an instruction execution unit and track and combing logic to combine a plurality of transactions into a single combined transaction. The track and combine logic comprises a transaction monitoring module to monitor an execution of a plurality of transactions by the instruction execution unit, each of the plurality of transactions comprising a transaction begin instruction, at least one operation instruction and a transaction end instruction. The track and combine logic further comprises a transaction combination module to identify, in view of the monitoring, a subset of the plurality of transactions to combine into a single combined transaction for execution on the processing device and to combine the identified subset of the plurality of transactions into the single combined transaction, the single combined transaction comprising a single transaction begin instruction, a plurality of operation instructions corresponding to the subset of the plurality of transactions and a single transaction end instruction.
摘要翻译： 处理装置包括指令执行单元和跟踪和组合逻辑以将多个事务组合成单个组合事务。 跟踪和组合逻辑包括事务监视模块，用于监视指令执行单元执行多个事务，所述多个事务中的每个事务包括事务开始指令，至少一个操作指令和事务结束指令。 轨道和组合逻辑还包括交易组合模块，用于鉴于监视，识别多个事务的子集以组合成单个组合事务以在处理设备上执行，并且将所识别的多个 事务转换为单个组合事务，单个组合事务包括单个事务开始指令，对应于多个事务的子集的多个操作指令和单个事务结束指令。
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4.发明申请公开(公告)号：US20150178086A1
公开(公告)日：2015-06-25
申请号：US14137218
申请日：2013-12-20
CPC分类号： G06F9/3806 , G06F9/3004 , G06F9/30087 , G06F9/382 , G06F9/3834 , G06F9/3836 , G06F11/0724 , G06F12/0806 , G06F12/0811 , G06F12/0842 , G06F12/0897 , G06F15/80
摘要： An apparatus and method for determining whether to execute an atomic operation locally or remotely. For example, one embodiment of a processor comprises: a decoder to decode an atomic operation on a local core; prediction logic on the local core to estimate a cost associated with execution of the atomic operation on the local core and a cost associated with execution of the atomic operation on a remote core; and the remote core to execute the atomic operation remotely if the prediction logic determines that the cost for execution on the local core is relatively greater than the cost for execution on the remote core; and the local core to execute the atomic operation locally if the prediction logic determines that the cost for local execution on the local core is relatively less than the cost for execution on the remote core.
摘要翻译： 一种用于确定是在本地还是远程执行原子操作的装置和方法。 例如，处理器的一个实施例包括：解码器，用于解码局部核心上的原子操作; 本地核心上的预测逻辑来估计与本地核心上的原子操作的执行相关的成本以及与在远程核心上执行原子操作相关联的成本; 以及所述远程核心，如果所述预测逻辑确定所述本地核上的执行成本相对大于所述远程核上的执行成本，则远程执行所述原子操作; 如果预测逻辑确定本地核心上的本地执行成本相对低于在远程核心上执行的成本，本地核心将在本地执行原子操作。
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公开(公告)号：US20140304477A1
公开(公告)日：2014-10-09
申请号：US13993034
申请日：2013-03-15
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/023 , G06F12/127 , Y02D10/13
摘要： A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines determine an object liveness value associated with a cache line in the processing device cache. The cache controller applies the object liveness value to a cache line eviction policy and evicts the cache line from the processing device cache based on the object liveness value and the cache line eviction policy.
摘要翻译： 处理设备包括处理设备高速缓存和高速缓存控制器。 高速缓存控制器启动高速缓存线驱逐过程并且确定确定与处理设备高速缓存中的高速缓存线相关联的对象活动值。 高速缓存控制器将对象活动值应用于高速缓存行驱逐策略，并基于对象活动性值和高速缓存行驱逐策略将缓存行从处理设备高速缓存中排除。
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公开(公告)号：US20140189247A1
公开(公告)日：2014-07-03
申请号：US13730507
申请日：2012-12-28
IPC分类号： G06F12/12
CPC分类号： G06F12/1009 , G06F12/123 , G06F12/127
摘要： An apparatus and method for implementing a scratchpad memory within a cache using priority hints. For example, a method according to one embodiment comprises: providing a priority hint for a scratchpad memory implemented using a portion of a cache; determining a page replacement priority based on the priority hint; storing the page replacement priority in a page table entry (PTE) associated with the page; and using the page replacement priority to determine whether to evict one or more cache lines associated with the scratchpad memory from the cache.
摘要翻译： 一种使用优先提示在高速缓存中实现暂存器存储器的装置和方法。 例如，根据一个实施例的方法包括：为使用高速缓存的一部分实现的暂存器存储器提供优先提示; 基于优先提示确定页面替换优先级; 将所述页面替换优先级存储在与所述页面相关联的页面表项（PTE）中; 以及使用页面替换优先级来确定是否从高速缓存驱逐与暂存器存储器相关联的一个或多个高速缓存行。
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公开(公告)号：US20150039841A1
公开(公告)日：2015-02-05
申请号：US13956609
申请日：2013-08-01
摘要： A processing device comprises an instruction execution unit and track and combing logic to combine a plurality of transactions into a single combined transaction. The track and combine logic comprises a transaction monitoring module to monitor an execution of a plurality of transactions by the instruction execution unit, each of the plurality of transactions comprising a transaction begin instruction, at least one operation instruction and a transaction end instruction. The track and combine logic further comprises a transaction combination module to identify, in view of the monitoring, a subset of the plurality of transactions to combine into a single combined transaction for execution on the processing device and to combine the identified subset of the plurality of transactions into the single combined transaction, the single combined transaction comprising a single transaction begin instruction, a plurality of operation instructions corresponding to the subset of the plurality of transactions and a single transaction end instruction.
摘要翻译： 处理装置包括指令执行单元和跟踪和组合逻辑以将多个事务组合成单个组合事务。 跟踪和组合逻辑包括事务监视模块，用于监视指令执行单元执行多个事务，所述多个事务中的每个事务包括事务开始指令，至少一个操作指令和事务结束指令。 轨道和组合逻辑还包括交易组合模块，用于鉴于监视，识别多个事务的子集以组合成单个组合事务以在处理设备上执行，并且将所识别的多个 事务转换为单个组合事务，单个组合事务包括单个事务开始指令，对应于多个事务的子集的多个操作指令以及单个事务结束指令。
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