公开(公告)号：US07519927B1

公开(公告)日：2009-04-14

申请号：US12166561

申请日：2008-07-02

申请人： John N. Hryckowian ,  Heidi L. Lagares-Vazquez ,  Ray Raphy ,  Alan Daniel Stigliani ,  Charles Vakirtzis

发明人： John N. Hryckowian ,  Heidi L. Lagares-Vazquez ,  Ray Raphy ,  Alan Daniel Stigliani ,  Charles Vakirtzis

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/62

摘要： Wiring structures and methods for integrated circuit designs which are adapted to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle time overlap violations in launch/capture clocking systems are provided, whereby the A/B/C (test/launch/capture) clock wire nets are designed using a five parallel track wire segment, in which the B clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, the C clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, and where the A test clock wire is represented as a single track comprising test signal wire disposed between the B and C signal wires.

摘要翻译： 提供了用于集成电路设计的接线结构和方法，其适于减少对发射捕获时钟对的金属变化影响，以便最小化发射/捕获时钟系统中的周期时间重叠违例，由此A / B / C（测试/发射 /捕获）时钟线网使用五个平行轨道线段设计，其中B时钟线表示为具有一个金属轨道和一个相邻隔离/屏蔽轨道的双轨道，C时钟线表示为双轨道 具有一个金属轨道和一个相邻的隔离/屏蔽轨道，并且其中A测试时钟线被表示为包括设置在B和C信号线之间的测试信号线的单个轨道。

公开(公告)号：US20060015836A1

公开(公告)日：2006-01-19

申请号：US11129785

申请日：2005-05-16

申请人： James Curtin ,  Kevin McIlvain ,  Ray Raphy ,  Douglas Search ,  Stephen Szulewski

发明人： James Curtin ,  Kevin McIlvain ,  Ray Raphy ,  Douglas Search ,  Stephen Szulewski

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5072 ,  G06F2217/84

摘要： More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one.. The NSRF value is calculated as equaling (ZWLM slack value +negative slack value)/ZWLM slack value=(1+(negative slack value/ZWLM slack value)), where ZWLM is a Zero Wire Load Model (ZWLM) value of timing wherein all wire parasitics are removed from consideration in the timing.

摘要翻译： NSRF（Negative Slack Recover Factor）提供了更多的“定时关闭效率”定时驱动的位置，通过实施新的净负载松弛路径来增强时序收敛行为。 这个新的权重不会基于路径中负的松弛的绝对量，而是基于必须恢复的路径的总净延迟加法器的比例或百分比，以实现定时关闭（零松弛） 。 在创建初始或先前的位置之后，然后为路径列表中的每个定时路径中的每个网络创建具有负松弛恢复因子（NSRF）的具有定时违规的路径列表，然后计算NSRF网 权重因子，并在NSRF默认值为1的情况下，在没有定时违规的路径列表中分配网络。NSRF值计算为相等（ZWLM松弛值+负松弛值）/ ZWLM松弛值=（ 1+（负松弛值/ ZWLM松弛值）），其中ZWLM是定时的零线负载模型（ZWLM）值，其中在定时中从考虑中去除所有线寄生。

公开(公告)号：US07823108B2

公开(公告)日：2010-10-26

申请号：US11934995

申请日：2007-11-05

申请人： James J. Curtin ,  Michael J. Cadigan, Jr. ,  Edward J. Hughes ,  Kevin M. Mcllvain ,  Jose L. Neves ,  Ray Raphy ,  Douglas S. Search

发明人： James J. Curtin ,  Michael J. Cadigan, Jr. ,  Edward J. Hughes ,  Kevin M. Mcllvain ,  Jose L. Neves ,  Ray Raphy ,  Douglas S. Search

IPC分类号： G06F17/50 ,  G06F9/44

CPC分类号： G06F17/5031

摘要： An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

摘要翻译： 使用Genie制造的集成电路芯片，Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。

公开(公告)号：US07356793B2

公开(公告)日：2008-04-08

申请号：US11129784

申请日：2005-05-16

申请人： James J. Curtin ,  Michael J. Cadigan, Jr. ,  Edward J. Hughes ,  Kevin M. McIlvain ,  Jose L. Neves ,  Ray Raphy ,  Douglas S. Search

发明人： James J. Curtin ,  Michael J. Cadigan, Jr. ,  Edward J. Hughes ,  Kevin M. McIlvain ,  Jose L. Neves ,  Ray Raphy ,  Douglas S. Search

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

摘要翻译： Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。

公开(公告)号：US07120888B2

公开(公告)日：2006-10-10

申请号：US10890463

申请日：2004-07-12

申请人： James J. Curtin ,  Ray Raphy ,  Stephen Szulewski

发明人： James J. Curtin ,  Ray Raphy ,  Stephen Szulewski

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Initial placement of the circuitry is determined in response to the composite net weight.

公开(公告)号：US20060010410A1

公开(公告)日：2006-01-12

申请号：US11129784

申请日：2005-05-16

申请人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin McIlvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

发明人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin McIlvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

摘要翻译： Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。

公开(公告)号：US20080052655A1

公开(公告)日：2008-02-28

申请号：US11876400

申请日：2007-10-22

申请人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin Mcllvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

发明人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin Mcllvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

IPC分类号： G06F17/50

CPC分类号： B62K25/286 ,  B62K3/02 ,  G06F17/5031

摘要： An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

摘要翻译： 使用Genie制造的集成电路芯片，Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。

公开(公告)号：US20080046850A1

公开(公告)日：2008-02-21

申请号：US11877200

申请日：2007-10-23

申请人： James Curtin ,  Kevin Mcllvain ,  Ray Raphy ,  Douglas Search ,  Stephen Szulewski

发明人： James Curtin ,  Kevin Mcllvain ,  Ray Raphy ,  Douglas Search ,  Stephen Szulewski

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/5072

摘要： An integrated circuit chip has more “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one. The NSRF value is calculated as equaling (ZWLM slack value+negative slack value)/ZWLM slack value=(1+(negative slack value/ZWLM slack value)), where ZWLM is a Zero Wire Load Model (ZWLM) value of timing wherein all wire parasitics are removed from consideration in the timing.

摘要翻译： NSRF（Negative Slack Recover Factor）提供集成电路芯片，通过实施新的净负载松弛路径净重以增强时序闭合性能，具有更多的“定时关闭效率”定时驱动位置。 这个新的权重不会基于路径中负的松弛的绝对量，而是基于必须恢复的路径的总净延迟加法器的比例或百分比，以实现定时关闭（零松弛） 。 在创建初始或先前的位置之后，然后为路径列表中的每个定时路径中的每个网络创建具有负松弛恢复因子（NSRF）的具有定时违规的路径列表，然后计算NSRF网 用于后续布局的权重因子，并且在没有定时违规的NSRF默认值为1的路径列表中分配网络。 计算NSRF值为ZWLM松弛值+负松弛值/ ZWLM松弛值=（1+（负松弛值/ ZWLM松弛值）），其中ZWLM是零线负载模型（ZWLM）定时值，其中 所有的电线寄生效应在时间上被忽略。

公开(公告)号：US20060277515A1

公开(公告)日：2006-12-07

申请号：US11466120

申请日：2006-08-22

申请人： James Curtin ,  Ray Raphy ,  Stephen Szulewski

发明人： James Curtin ,  Ray Raphy ,  Stephen Szulewski

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Initial placement of the circuitry is determined in response to the composite net weight.

摘要翻译： 一种用于在集成电路设计期间确定电路布置的方法。 该方法包括访问识别电路连接的网络列表。 在网络列表内的定时路径中将多个单独的净权重分配给网络，各个净权重与物理设计参数无关。 对于所述定时路径确定复合净重，所述复合净重是响应于所述多个个体净重。 响应于复合净重确定电路的初始放置。

公开(公告)号：US20060010415A1

公开(公告)日：2006-01-12

申请号：US10890463

申请日：2004-07-12

申请人： James Curtin ,  Ray Raphy ,  Stephen Szulewski

发明人： James Curtin ,  Ray Raphy ,  Stephen Szulewski

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method for determining placement of circuitry during integrated circuit design. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list, the individual net weights being valid irrespective of physical design parameters. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Initial placement of the circuitry is determined in response to the composite net weight.