Chip having timing analysis of paths performed within the chip during the design process
    1.
    发明授权
    Chip having timing analysis of paths performed within the chip during the design process 有权
    芯片具有在设计过程中在芯片内执行的路径的定时分析

    公开(公告)号:US07823108B2

    公开(公告)日:2010-10-26

    申请号:US11934995

    申请日:2007-11-05

    IPC分类号: G06F17/50 G06F9/44

    CPC分类号: G06F17/5031

    摘要: An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

    摘要翻译: 使用Genie制造的集成电路芯片,Genie是一种描述的计算机芯片设计工具,可以分析整个端点报告中包含的数据,计算基于共享段的路径之间的关系,并将图形显示给设计者。 具体来说,Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部,并被标记为Hub。 将定时岛作为一棵树,岛上的中心将是树干。 如果树干被树干砍下来,所有的树枝,四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障,并且修复程序会逐渐转移到每个从集线器上散落的段。