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    System and medium for placement which maintain optimized timing behavior, while improving wireability potential
    2.
    发明授权
    System and medium for placement which maintain optimized timing behavior, while improving wireability potential 有权
    用于放置的系统和介质，其保持优化的定时行为，同时提高可线性潜力

    公开(公告)号：US07921398B2

    公开(公告)日：2011-04-05

    申请号：US12047382

    申请日：2008-03-13

    申请人： James J. Curtin ,  Jose L. Neves ,  Douglas S. Search

    发明人： James J. Curtin ,  Jose L. Neves ,  Douglas S. Search

    IPC分类号： G06F17/50 ,  G06F19/00

    CPC分类号： G06F17/5031 ,  G06F17/5072 ,  G06F2217/84

    摘要： A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.

    摘要翻译： 提出了一种确定集成电路设计过程中电路布局的方法。 该方法包括访问识别电路连接的网络列表。 在网络列表内的定时路径中将多个单独的净权重分配给网络。 对于所述定时路径确定复合净重，所述复合净重是响应于所述多个个体净重。 与此同时，利用我们的新的同时进行的改进方法是有利的，以通过额外的时序优化和净重映射修改步骤来改善所述设计的可线性。

    Method for eliminating negative slack in a netlist via transformation and slack categorization
    3.
    发明授权
    Method for eliminating negative slack in a netlist via transformation and slack categorization 有权
    通过转换和松散分类消除网表中的负松弛的方法

    公开(公告)号：US07810062B2

    公开(公告)日：2010-10-05

    申请号：US11853573

    申请日：2007-09-11

    申请人： James J. Curtin ,  William E. Dougherty, Jr. ,  Jose L. Neves ,  Douglas S. Search

    发明人： James J. Curtin ,  William E. Dougherty, Jr. ,  Jose L. Neves ,  Douglas S. Search

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F2217/84

    摘要： A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.

    摘要翻译： 用于消除表示芯片设计的网表中的负松弛的方法使用设计的定时环境来在逻辑和物理合成阶段将信息叠加到设计环境上。 重叠的定时信息确定哪个网表转换为负消除消除提供了最大的杠杆作用，以及为每个设计调整的创建动态变换配方的方法。 该方法进一步提供消极消除的上限，以防止网表变换被应用于超出改进设计能力的情况。

    System and Medium for Placement Which Maintain Optimized Timing Behavior, While Improving Wireability Potential
    6.
    发明申请
    System and Medium for Placement Which Maintain Optimized Timing Behavior, While Improving Wireability Potential 有权
    系统和介质放置，保持优化的时序行为，同时提高可接线性潜力

    公开(公告)号：US20080163149A1

    公开(公告)日：2008-07-03

    申请号：US12047382

    申请日：2008-03-13

    申请人： James J. Curtin ,  Jose L. Neves ,  Douglas S. Search

    发明人： James J. Curtin ,  Jose L. Neves ,  Douglas S. Search

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031 ,  G06F17/5072 ,  G06F2217/84

    摘要： A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.

    摘要翻译： 提出了一种确定集成电路设计过程中电路布局的方法。 该方法包括访问识别电路连接的网络列表。 在网络列表内的定时路径中将多个单独的净权重分配给网络。 对于所述定时路径确定复合净重，所述复合净重是响应于所述多个个体净重。 与此同时，利用我们的新的同时进行的改进方法是有利的，以通过附加的时序优化和净重映射修改步骤来提高所述设计的可线性。

    Negative slack recoverability factor—a net weight to enhance timing closure behavior
    7.
    发明授权
    Negative slack recoverability factor—a net weight to enhance timing closure behavior 有权
    负松弛恢复因子 - 净重以增强时序收敛行为

    公开(公告)号：US07305644B2

    公开(公告)日：2007-12-04

    申请号：US11129785

    申请日：2005-05-16

    申请人： James J. Curtin ,  Kevin M. McIlvain ,  Ray Raphy ,  Douglas S. Search ,  Stephen Szulewski

    发明人： James J. Curtin ,  Kevin M. McIlvain ,  Ray Raphy ,  Douglas S. Search ,  Stephen Szulewski

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5031 ,  G06F17/5072 ,  G06F2217/84

    摘要： More “timing closure efficient” Timing Driven Placements by implementing our new net weight for negative slack paths to enhance timing closure behavior is provided by a NSRF (Negative Slack Recover Factor). This new weight would not be based on the absolute amount of negative slack in a path, but rather it would be based on the proportion or percentage of the path's total net delay adder that must be recovered in order to achieve timing closure (zero slack). After an initial or previous placement has been created, then a list of paths with timing violations with a Negative Slack Recover Factor (NSRF) is created for each net in each of the timing paths on the list of paths, and then calculating a NSRF net weight factor for use in subsequent placements and also assigning nets in the list of paths with no timing violations a NSRF default value of one. The NSRF value is calculated as equaling (ZWLM slack value+negative slack value)/ZWLM slack value=(1+(negative slack value/ZWLM slack value)), where ZWLM is a Zero Wire Load Model (ZWLM) value of timing wherein all wire parasitics are removed from consideration in the timing.

    摘要翻译： NSRF（Negative Slack Recover Factor）提供了更多的“定时关闭效率”定时驱动的位置，通过实施新的净负载松弛路径来增强时序收敛行为。 这个新的权重不会基于路径中负的松弛的绝对量，而是基于必须恢复的路径的总净延迟加法器的比例或百分比，以实现定时关闭（零松弛） 。 在创建初始或先前的位置之后，然后为路径列表中的每个定时路径中的每个网络创建具有负松弛恢复因子（NSRF）的具有定时违规的路径列表，然后计算NSRF网 用于后续布局的权重因子，并且在没有定时违规的NSRF默认值为1的路径列表中分配网络。 计算NSRF值为ZWLM松弛值+负松弛值/ ZWLM松弛值=（1+（负松弛值/ ZWLM松弛值）），其中ZWLM是零线负载模型（ZWLM）定时值，其中 所有的电线寄生效应在时间上被忽略。

    Method for netlist path characteristics extraction
    8.
    发明授权
    Method for netlist path characteristics extraction 失效
    网表路径特征提取方法

    公开(公告)号：US07290233B2

    公开(公告)日：2007-10-30

    申请号：US11129786

    申请日：2005-05-16

    申请人： James J. Curtin ,  Kevin M. McIlvain ,  Ray Raphy ,  Douglas S. Search ,  Stephen Szulewski

    发明人： James J. Curtin ,  Kevin M. McIlvain ,  Ray Raphy ,  Douglas S. Search ,  Stephen Szulewski

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A circuit design method utilizes existing late mode worst case slack calculation functions inherent in timing path trace algorithms which only need to record the worst arrival and worst required arrival times at each netlist node as traced paths. Because of this, most individual path tracing is curtailed due to the likelihood that a more critical arrival or required arrival time has already been recorded at a given netlist node. Worst case slacks are then determined by subtracting the worst case arrival time from the worst case required arrival time. In this manner, worst case slack values are calculated for the entire netlist within a reasonable amount of time. The method uses these existing functions by querying the worst case slack at each netlist node under varied timing model scenarios. These varied timing model scenarios include altering the cell and net delays and arrival times in the model. Then, with the worst case slacks from the varied timing model scenarios in hand, the required priority factors, recoverability and path composition factors are computed by comparing the differences in the worst case slack at each netlist node.

    摘要翻译： 电路设计方法利用定时路径跟踪算法中固有的现有的后期模式最差情况松弛计算功能，其仅需要记录每个网表节点处的最差到达和最差的到达时间作为跟踪路径。 因此，由于在给定的网表节点已经记录了更为关键的到达时间或必需的到达时间的可能性，大多数单独的路径跟踪被限制。 然后通过从最坏情况所需的到达时间减去最坏情况的到达时间来确定最差的情况。 以这种方式，在合理的时间内，对整个网表计算最坏情况的松弛值。 该方法通过在不同的时序模式情景下查询每个网表节点处最坏情况的松弛来使用这些现有的功能。 这些不同的时间模型情景包括改变模型中的细胞和净延迟和到达时间。 然后，随着手段中不同时间模式情况的最坏情况的松动，通过比较每个网表节点最差情况下的差异，计算所需的优先级因素，可恢复性和路径组成因子。

    Combination cover for golf club bags and towel
    9.
    发明授权
    Combination cover for golf club bags and towel 失效
    组合盖高尔夫球包和毛巾

    公开(公告)号：US5407723A

    公开(公告)日：1995-04-18

    申请号：US117472

    申请日：1993-09-07

    申请人： James J. Curtin

    发明人： James J. Curtin

    IPC分类号： A63B55/00 ,  B32B9/00

    CPC分类号： A63B55/406 ,  Y10T428/23907 ,  Y10T428/24008 ,  Y10T428/24033 ,  Y10T428/24215 ,  Y10T428/2424

    摘要： A combination towel and cover for a golf club bag. The device is a flat, foldable material having a water repellant side and a water absorbing towel side. Fastening members are positioned along selected peripheral edges of the device to hold it in a folded configuration. When fully folded, it is attachable by a clamp to a golf club bag. When unfolded, it is attachable by snapping the fastening members onto the snaps built into golf club bags such that its towel side is exposed for use. When so disposed, it may be flipped over the clubs to protect them during inclement weather, but the golfer may still reach under the device to use its towel side even when it has been flipped over. Preselected edges of the towel part of the device are unattached to the water repellant side to facilitate placing hands to be dried on opposite sides of the towel.

    摘要翻译： 高尔夫球包的组合毛巾和盖子。 该装置是具有防水侧和吸水毛巾侧的平坦的可折叠材料。 紧固构件沿着装置的选定的外围边缘定位以将其保持在折叠构型。 当完全折叠时，它可以通过夹具附接到高尔夫球杆袋。 当展开时，通过将紧固构件卡扣到内置于高尔夫球杆袋中的卡扣上，使得其毛巾侧被暴露以供使用可附接。 当这样处理时，它可以翻转在俱乐部上以在恶劣天气期间保护它们，但是即使被翻转，高尔夫球手仍然可以到达设备下方使用其毛巾侧。 装置的毛巾部分的预选边缘未附着在防水剂侧，以便于将手在毛巾的相对侧上放置干燥。

    Chip having timing analysis of paths performed within the chip during the design process
    10.
    发明授权
    Chip having timing analysis of paths performed within the chip during the design process 有权
    芯片具有在设计过程中在芯片内执行的路径的定时分析

    公开(公告)号：US07823108B2

    公开(公告)日：2010-10-26

    申请号：US11934995

    申请日：2007-11-05

    申请人： James J. Curtin ,  Michael J. Cadigan, Jr. ,  Edward J. Hughes ,  Kevin M. Mcllvain ,  Jose L. Neves ,  Ray Raphy ,  Douglas S. Search

    发明人： James J. Curtin ,  Michael J. Cadigan, Jr. ,  Edward J. Hughes ,  Kevin M. Mcllvain ,  Jose L. Neves ,  Ray Raphy ,  Douglas S. Search

    IPC分类号： G06F17/50 ,  G06F9/44

    CPC分类号： G06F17/5031

    摘要： An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

    摘要翻译： 使用Genie制造的集成电路芯片，Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。