THREE-PHASE MOTOR DRIVER WITH BUILT-IN DISCRETE MOSFETS

    公开(公告)号:US20240321824A1

    公开(公告)日:2024-09-26

    申请号:US18187300

    申请日:2023-03-21

    摘要: Circuits and devices for a motor driver are described. A hybrid integrated circuit (IC) can include a driver IC, a first IC, and a plurality of second ICs. The first IC can include a plurality of high-side metal-oxide-semiconductor field-effect transistors (MOSFETs). The first IC can further include a common drain terminal connected to drains of the plurality of high-side MOSFETs. Each one of the plurality of second ICs can include a respective low-side MOSFET. The hybrid IC can further include a first set of bonding wires connecting the driver IC to the first IC. The hybrid IC can further include a second set of bonding wires connecting the driver IC to the plurality of second ICs. The hybrid IC can further include a third set of bonding wires connecting the first IC to the plurality of second ICs.

    INTEGRATED CIRCUIT WITH PROTECTIVE ELEMENT
    4.
    发明公开

    公开(公告)号:US20240274595A1

    公开(公告)日:2024-08-15

    申请号:US18496529

    申请日:2023-10-27

    摘要: An integrated circuit is presented. The integrated circuit includes an internal circuit; a contact pad; and a protective element coupled between the internal circuit and the contact pad. The protective element is operable in a first state or a second state. In the first state the protective element passes a current between the internal circuit and the contact pad. When the current is above a threshold value the protective element changes from the first state to the second state to reduce or prevent the current from flowing between the internal circuit and the contact pad. The protective element may be used to prevent damage to an external circuit connected to the integrated circuit.

    FLYING CAPACITOR STARTUP CIRCUIT FOR MULTI-LEVEL VOLTAGE CONVERTER

    公开(公告)号:US20240250609A1

    公开(公告)日:2024-07-25

    申请号:US18156766

    申请日:2023-01-19

    IPC分类号: H02M3/07 H02M1/00 H02M1/36

    CPC分类号: H02M3/07 H02M1/0095 H02M1/36

    摘要: Apparatuses, devices, and methods for operating a multi-level voltage converter are described. A semiconductor device can include a circuit, where the circuit can include a plurality of current sources. The circuit can be configured to measure a flying capacitor voltage across a flying capacitor of a multi-level voltage converter. The circuit can be further configured to compare the flying capacitor voltage with a voltage level equivalent to an intermediate voltage that is between ground and an input voltage being provided to the multi-level voltage converter. The circuit can be further configured to, based on a result of the comparison, switch a current source among the plurality of current sources to maintain the flying capacitor voltage at the intermediate voltage.

    SYSTEMS AND METHODS FOR PLUNGER MOVEMENT DETECTION

    公开(公告)号:US20240247954A1

    公开(公告)日:2024-07-25

    申请号:US18156728

    申请日:2023-01-19

    IPC分类号: G01D5/20 G01R19/10 G01R19/165

    摘要: Systems and methods for detecting a plunger movement condition with respect to a solenoid coil are described. A method may include generating a first derivative signal waveform of a current flowing in the solenoid coil, identifying whether there is at least one zero crossing point in the first derivative signal waveform, and detecting the plunger movement condition according to an identification result indicating whether there is at least one zero crossing point in the first derivative signal waveform.

    Circuit and method for determining a delay of a delay circuit

    公开(公告)号:US12028076B1

    公开(公告)日:2024-07-02

    申请号:US18174823

    申请日:2023-02-27

    IPC分类号: H03K5/135 H03K5/00

    CPC分类号: H03K5/135 H03K2005/00019

    摘要: A circuit and corresponding method for determining a delay are presented. The circuit includes a delay circuit, a feedback circuit and a controller. The delay circuit receives an input signal having an input edge and provides an output signal having an output edge. The input edge and the output edge are separated by a delay. The feedback circuit causes the delay circuit to generate a series of consecutive output pulses. The controller sets the delay to a first delay value and measures a first period of output pulses; sets the delay to a second delay value and measure a second period of output pulses. The controller then calculates the delay based on a difference between the first period and the second period.

    COMMON GATE DRIVE CIRCUIT FOR SWITCHING HIGH VOLTAGE DEVICE

    公开(公告)号:US20240195401A1

    公开(公告)日:2024-06-13

    申请号:US18064340

    申请日:2022-12-12

    发明人: Tetsuo SATO

    IPC分类号: H03K17/042

    CPC分类号: H03K17/04206 H03K17/0822

    摘要: Semiconductor devices for driving transistors in a power device are described. A semiconductor device can include a voltage source configured to provide a fixed bias voltage to a first device implemented as a common gate device. The semiconductor device can further include a second device connected in series with the first device. The current output of the second device can be connected to a source terminal of the first device. The semiconductor device can further include a driver configured to drive the second device to perform current control on the first device.

    Method and system for continuously verifying integrity of secure instructions during runtime

    公开(公告)号:US12001557B2

    公开(公告)日:2024-06-04

    申请号:US17125208

    申请日:2020-12-17

    IPC分类号: G06F21/57 H04L9/32

    摘要: Example implementations include a method of requesting an instruction block associated with one or more instructions and located at one or more addresses of a system memory, obtaining the instruction block from the system memory, generating a hash of the instruction block, obtaining an expected hash associated with the instruction block, comparing the expected hash with the generated hash, in accordance with a determination that the expected hash matches the generated hash, generating a first validation response associated with the instruction block. Example implementations also include a method of obtaining a secure instruction image including an expected hash associated with an instruction block, the instruction block associated with one or more instructions and located at one or more addresses of a system memory, storing the secure instruction image at a configuration register, and enabling the hardware controller to perform one or more hashing operations associated with the instruction block during runtime of a system processor.