公开(公告)号：US08399924B2

公开(公告)日：2013-03-19

申请号：US13160759

申请日：2011-06-15

Applicant: Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

公开(公告)号：US20110309440A1

公开(公告)日：2011-12-22

申请号：US13160759

申请日：2011-06-15

Applicant: Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

Inventor： Pinghai Hao ,  Sameer Pendharkar ,  Binghua Hu ,  Qingfeng Wang

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

Abstract translation: 包含扩展漏极MOS晶体管的集成电路可以通过形成具有掩模手指的沟道区域的漂移区域注入掩模来形成，并且延伸到源极/沟道有源区，但不延伸到漏极接触有源区。 通过暴露的指状物注入的掺杂剂在掩模指下面的衬底中形成横向掺杂条纹。 栅极下方的漂移区域的平均掺杂密度比漏极接触有效面积处的漂移区域的平均掺杂密度小至少25％。 在一个实施例中，掺杂剂横向漫射以形成连续漂移区域。 在另一个实施例中，横向掺杂条纹之间的衬底材料与横向掺杂条纹保持相反的导电类型。

公开(公告)号：US07785974B2

公开(公告)日：2010-08-31

申请号：US11474824

申请日：2006-06-26

Applicant: Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

Inventor： Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

IPC: H01L21/331

CPC classification number: H01L21/74 ,  H01L21/2253 ,  H01L21/8249 ,  H01L29/66272

Abstract: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.

Abstract translation: 一种用于形成双极晶体管器件的方法包括提供半导体衬底。 在半导体基板上形成氧化物层。 图案化氧化物层以形成露出半导体衬底的一部分的开口。 通过开口将诸如锑的掺杂剂注入到半导体衬底中以形成掩埋层。 去除掩模层的上部以限定薄掩模层。 进行掩埋层扩散处理以在注入的掺杂剂中驱动，同时减轻凹陷形成。

公开(公告)号：US20080085569A1

公开(公告)日：2008-04-10

申请号：US11531103

申请日：2006-09-12

Applicant: Qingfeng Wang ,  Sameer P. Pendharkar ,  Binghua Hu

Inventor： Qingfeng Wang ,  Sameer P. Pendharkar ,  Binghua Hu

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L29/0649 ,  H01L29/8605

Abstract: Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.

Abstract translation: 实施例提供了用于电监测半导体器件中的沟槽深度的方法和装置。 为了电测量沟槽深度，可以在半导体衬底上的深阱区域中形成夹持电阻器。 然后可以在夹持电阻器中形成沟槽。 沟槽深度可以通过夹持电阻器的电气测试来确定。 所公开的方法和装置可以跨晶片提供统计数据分析，并且可以在作为过程监视器的生产划线中实施。 所公开的方法也可用于确定LDMOS晶体管的器件性能。 LDMOS晶体管的导通电阻（Rdson）可以与沟槽深度的电测量相关。

公开(公告)号：US07112953B2

公开(公告)日：2006-09-26

申请号：US11049138

申请日：2005-02-02

Applicant: Xinfen Chen ,  Xiaoju Wu ,  John K. Arch ,  Qingfeng Wang

Inventor： Xinfen Chen ,  Xiaoju Wu ,  John K. Arch ,  Qingfeng Wang

IPC: G01R31/02

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure in, on or over a substrate of a semiconductor device, the buried layer test structure including a first test buried layer located in or on the substrate, the first test buried layer shifted a predetermined distance with respect to a first test feature. The buried layer test structure further includes a second test buried layer lodated in the substrate, the second test buried layer shifted a predetermined but different distance with respect to a second test feature. The method for monitoring the shift in the buried layer may further include applying a test signal to the buried layer test structure to determine an actual shift relative to the predetermined shift.

Abstract translation: 本发明提供了一种用于监测半导体器件中的掩埋层的偏移的方法。 用于监测掩埋层中的偏移的方法以及其它步骤包括在半导体器件的衬底上或上方形成掩埋层测试结构，所述掩埋层测试结构包括位于第一测试掩埋层中或其上的第一测试掩埋层 第一测试掩埋层相对于第一测试特征偏移预定距离。 掩埋层测试结构还包括置于衬底中的第二测试掩埋层，第二测试掩埋层相对于第二测试特征偏移预定但不同的距离。 用于监测掩埋层中的偏移的方法还可以包括将测试信号施加到掩埋层测试结构以确定相对于预定位移的实际偏移。

公开(公告)号：US07989232B2

公开(公告)日：2011-08-02

申请号：US11531103

申请日：2006-09-12

Applicant: Qingfeng Wang ,  Sameer P. Pendharkar ,  Binghua Hu

Inventor： Qingfeng Wang ,  Sameer P. Pendharkar ,  Binghua Hu

IPC: H01L21/66 ,  H01L27/07

CPC classification number: H01L22/12 ,  H01L29/0649 ,  H01L29/8605

Abstract: Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.

Abstract translation: 实施例提供了用于电监测半导体器件中的沟槽深度的方法和装置。 为了电测量沟槽深度，可以在半导体衬底上的深阱区域中形成夹持电阻器。 然后可以在夹持电阻器中形成沟槽。 沟槽深度可以通过夹持电阻器的电气测试来确定。 所公开的方法和装置可以跨晶片提供统计数据分析，并且可以在作为过程监视器的生产划线中实现。 所公开的方法也可用于确定LDMOS晶体管的器件性能。 LDMOS晶体管的导通电阻（Rdson）可以与沟槽深度的电测量相关。

公开(公告)号：US07713825B2

公开(公告)日：2010-05-11

申请号：US11753789

申请日：2007-05-25

Applicant: Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Qingfeng Wang

Inventor： Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Qingfeng Wang

IPC: H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 9° or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

Abstract translation: 示例性实施例提供了用于在半导体中形成掺杂区域的制造方法。 具体地，可以通过使用图案化光致抗蚀剂（PR）层作为掩模的多个离子注入工艺来形成掺杂区域。 可以通过去除硬烘烤步骤以改善图案化PR层的轮廓，使用硬烘焙光刻工艺来形成图案化的PR层。 多个离子注入工艺可以以下列顺序执行：使用高能量注入第一掺杂物种; 使用减少的能量和增加的植入角度（例如，约9°或更高）注入第一掺杂物种类; 以及使用减少的能量注入第二掺杂剂物质。 在各种实施例中，掺杂区域可以用作LDMOS晶体管的双扩散区域。

公开(公告)号：US20060038553A1

公开(公告)日：2006-02-23

申请号：US11049138

申请日：2005-02-02

Applicant: Xinfen Chen ,  Xiaoju Wu ,  John Arch ,  Qingfeng Wang

Inventor： Xinfen Chen ,  Xiaoju Wu ,  John Arch ,  Qingfeng Wang

IPC: G01R31/28

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device and a method for manufacturing an integrated circuit using the method for monitoring the shift in the buried layer. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure (200) in, on or over a substrate (210) of a semiconductor device, the buried layer test structure (200) including a first test buried layer (230a) located in or on the substrate (210), the first test buried layer (230a) shifted a predetermined distance with respect to a first test feature (240a). The buried layer test structure (200) further includes a second test buried layer (230b) located in the substrate (210), the second test buried layer (23b) shifted a predetermined but different distance with respect to a second test feature (240b). The method for monitoring the shift in the buried layer may further include applying a test signal to the buried layer test structure (200) to determine an actual shift of the first test buried layer (230a) and the second test buried layer (230b) relative to the predetermined shift of the first and second test buried layers (230a and 230b).

Abstract translation: 本发明提供了一种用于监测半导体器件中的掩埋层的偏移的方法以及使用用于监测掩埋层中的偏移的方法来制造集成电路的方法。 用于监测掩埋层中的偏移的方法以及其他步骤包括在半导体器件的衬底（210）中或之上形成掩埋层测试结构（200），所述掩埋层测试结构（200）包括 第一测试掩埋层（230a）位于衬底（210）中或衬底（210）上，第一测试掩埋层（230a）相对于第一测试特征（240a）移动预定距离。 掩埋层测试结构（200）还包括位于衬底（210）中的第二测试掩埋层（230b），第二测试掩埋层（23b）相对于第二测试特征（预定但不同的距离）移动 240 b）。 用于监测掩埋层中的偏移的方法还可以包括将测试信号施加到掩埋层测试结构（200）以确定第一测试掩埋层（230a）和第二测试掩埋层（230b）的实际偏移 ）相对于第一和第二测试掩埋层（230a和230b）的预定位移。

公开(公告)号：US20070298579A1

公开(公告)日：2007-12-27

申请号：US11474824

申请日：2006-06-26

Applicant: Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

Inventor： Binghua Hu ,  Yu-En Hsu ,  Qingfeng Wang

IPC: H01L21/331 ,  H01L21/425

CPC classification number: H01L21/74 ,  H01L21/2253 ,  H01L21/8249 ,  H01L29/66272

Abstract: A method for forming a bipolar transistor device includes providing a semiconductor substrate. An oxide layer is formed on the semiconductor substrate. The oxide layer is patterned to form an opening that exposes a portion of the semiconductor substrate. A dopant, such as antimony, is implanted into the semiconductor substrate through the opening to form a buried layer. An upper portion of the mask layer is removed to define a thin mask layer. A buried layer diffusion process is performed to drive in the implanted dopants while mitigating recess formation.

Abstract translation: 一种用于形成双极晶体管器件的方法包括提供半导体衬底。 在半导体基板上形成氧化物层。 图案化氧化物层以形成露出半导体衬底的一部分的开口。 通过开口将诸如锑的掺杂剂注入到半导体衬底中以形成掩埋层。 去除掩模层的上部以限定薄掩模层。 进行掩埋层扩散处理以在注入的掺杂剂中驱动，同时减轻凹陷形成。

公开(公告)号：US20080293206A1

公开(公告)日：2008-11-27

申请号：US11753789

申请日：2007-05-25

Applicant: Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Qingfeng Wang

Inventor： Binghua Hu ,  Sameer P. Pendharkar ,  Bill A. Wofford ,  Qingfeng Wang

IPC: H01L21/336

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

Abstract: Exemplary embodiments provide manufacturing methods for forming a doped region in a semiconductor. Specifically, the doped region can be formed by multiple ion implantation processes using a patterned photoresist (PR) layer as a mask. The patterned PR layer can be formed using a hard-bakeless photolithography process by removing a hard-bake step to improve the profile of the patterned PR layer. The multiple ion implantation processes can be performed in a sequence of, implanting a first dopant species using a high energy; implanting the first dopant species using a reduced energy and an increased implant angle (e.g., about 90 or higher); and implanting a second dopant species using a reduced energy. In various embodiments, the doped region can be used as a double diffused region for LDMOS transistors.

Abstract translation: 示例性实施例提供了用于在半导体中形成掺杂区域的制造方法。 具体地，可以通过使用图案化光致抗蚀剂（PR）层作为掩模的多个离子注入工艺来形成掺杂区域。 可以通过去除硬烘烤步骤以改善图案化PR层的轮廓，使用硬烘焙光刻工艺来形成图案化的PR层。 多个离子注入工艺可以以下列顺序执行：使用高能量注入第一掺杂物种; 使用减少的能量和增加的植入角度（例如，约90或更高）注入第一掺杂物种类; 以及使用减少的能量注入第二掺杂剂物质。 在各种实施例中，掺杂区域可以用作LDMOS晶体管的双扩散区域。