公开(公告)号：US20080090020A1

公开(公告)日：2008-04-17

申请号：US11951244

申请日：2007-12-05

Applicant: Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

Inventor： Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

IPC: B05D3/04 ,  C23C14/35

CPC classification number: H01L28/40

Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract translation: 描述了用于制造金属 - 绝缘体 - 金属电容器的方法。 在基板上形成第一金属层。 在第一金属层的表面进行等离子体处理。 然后，依次在第一金属层上形成第一氧化物层，氮化物层和第二氧化物层。 此后，在第二氧化物层上形成第二金属层。 第二金属层，第二氧化物层，氮化物层，第一氧化物层和第一金属层被定义为形成金属 - 绝缘体 - 金属电容器。

公开(公告)号：US20070218626A1

公开(公告)日：2007-09-20

申请号：US11377160

申请日：2006-03-15

Applicant: Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

Inventor： Ping-Wei Lin ,  Chin-Chia Wu ,  Chao-Sheng Chiang

IPC: H01L21/8242

CPC classification number: H01L28/40

Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract translation: 描述了用于制造金属 - 绝缘体 - 金属电容器的方法。 在基板上形成第一金属层。 在第一金属层的表面进行等离子体处理。 然后，依次在第一金属层上形成第一氧化物层，氮化物层和第二氧化物层。 此后，在第二氧化物层上形成第二金属层。 第二金属层，第二氧化物层，氮化物层，第一氧化物层和第一金属层被定义为形成金属 - 绝缘体 - 金属电容器。

公开(公告)号：US20050186796A1

公开(公告)日：2005-08-25

申请号：US10784186

申请日：2004-02-24

Applicant: Ping-Wei Lin ,  Chao-Sheng Chiang ,  Kuo-Chuan Kuo

Inventor： Ping-Wei Lin ,  Chao-Sheng Chiang ,  Kuo-Chuan Kuo

IPC: H01L21/311 ,  H01L21/316 ,  H01L21/469 ,  H01L21/473 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76837

Abstract: A method for gap filling between metal-metal lines is provided so that a first dielectric layer forms on a surface and side wall of a plurality of metal lines thereon which is called partially HDP deposition. Then, a portion of the first dielectric layer is removed by a high-density plasma with Ar/O2 to sputter so that a portion of side wall of metal lines is exposed. Afterwards, a second dielectric layer is formed on the first dielectric layer by a method of high density plasma oxide deposition so that the metal lines are completely covered.

Abstract translation: 提供金属 - 金属线之间的间隙填充的方法，使得第一介电层在其上的多个金属线的表面和侧壁上形成，称为部分HDP沉积。 然后，通过具有Ar / O 2 N的高密度等离子体去除第一介电层的一部分，以溅射金属线的侧壁的一部分。 之后，通过高密度等离子体氧化物沉积的方法在第一介电层上形成第二电介质层，使得金属线被完全覆盖。

公开(公告)号：US06261930B1

公开(公告)日：2001-07-17

申请号：US09287440

申请日：1999-04-07

Applicant: Ping-Wei Lin ,  Jui-Ping Li ,  Ming-Kuan Kao ,  Yi-Shin Chang

Inventor： Ping-Wei Lin ,  Jui-Ping Li ,  Ming-Kuan Kao ,  Yi-Shin Chang

IPC: H01L2120

CPC classification number: H01L28/84

Abstract: An irradiation process method for forming polysilicon layer is disclosed. The method includes firstly forming an alpha-silicon layer on substrate. Then the temperature of the UHV-CVD chamber is increased and the wafer is sent into the chamber. Gas is then intermittently conducted into the vacuum-chamber apparatus. While increasing the temperature of the vacuum-chamber apparatus, the whole throughput thus increases and the process-time for the polysilicon layer thus decreases. Finally, the electrical capacity thus increases by forming the polysilicon layer.

Abstract translation: 公开了一种用于形成多晶硅层的照射处理方法。 该方法包括首先在基底上形成α-硅层。 然后，UHV-CVD室的温度升高，将晶片送入室内。 然后将气体间歇地传导到真空室装置中。 在增加真空室装置的温度的同时，整体生产量因此增加，因此多晶硅层的处理时间减少。 最后，通过形成多晶硅层而增加电容量。

公开(公告)号：US06191003B1

公开(公告)日：2001-02-20

申请号：US09487661

申请日：2000-01-19

Applicant: Ping-wei Lin ,  Chien-hung Chen ,  Jui-ping Li ,  Yen-jung Chang

Inventor： Ping-wei Lin ,  Chien-hung Chen ,  Jui-ping Li ,  Yen-jung Chang

IPC: H01L2176

CPC classification number: H01L21/3212 ,  H01L21/76224

Abstract: A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer with an enough thickness is deposited on the surface of the semiconductor substrate to overfill the trench. At least one dimple is undesirably developed on the polycrystalline silicon layer during the polycrystalline silicon deposition. Then, an oxide layer with an enough thickness is formed on the polycrystalline silicon layer to overfill the at least one dimple. Next, the polycrystalline silicon layer is partially oxidized so as to transform the upper portion thereof into a polysilicon oxide layer. As a result of a non-uniform distribution of the oxidization rate, the bottom surface of the polysilicon oxide layer, i.e. the interface between the polysilicon oxide layer and the non-oxidized portion of the polycrystalline silicon layer, is substantially planar. Finally, the oxide layer and the polysilicon oxide layer are both removed so as to expose the substantially planar polycrystalline silicon layer.

Abstract translation: 用于平坦化沉积在沟槽上的多晶硅层的方法，其形成在半导体衬底上，包括以下步骤。 首先，在半导体衬底的表面上沉积具有足够厚度的多晶硅层，以过度填充沟槽。 在多晶硅沉积期间，至少一个凹坑不希望地在多晶硅层上显影​​。 然后，在多晶硅层上形成足够厚度的氧化物层，以过度填充至少一个凹坑。 接下来，多晶硅层被部分氧化，以将其上部变换成多晶硅氧化物层。 由于氧化速率的不均匀分布的结果，多晶硅氧化物层的底表面，即多晶硅氧化物层和多晶硅层的未氧化部分之间的界面基本上是平面的。 最后，去除氧化物层和多晶硅氧化物层，以暴露基本平坦的多晶硅层。

公开(公告)号：US06171904B2

公开(公告)日：2001-01-09

申请号：US09352411

申请日：1999-07-14

Applicant: Ping-Wei Lin ,  Jui-Ping Li ,  Ming-Kuan Kao

Inventor： Ping-Wei Lin ,  Jui-Ping Li ,  Ming-Kuan Kao

IPC: H01L218242

CPC classification number: H01L28/84 ,  H01L27/1085 ,  Y10S438/964

Abstract: The present invention relates to a method for forming rugged polysilicon capacitance electrodes uses for dynamic random access memory processes is disclosed. The method is capable in reducing process time, enhancing yield, and saving production cost. Wherein, the process of the present invention comprises: firstly, a semiconductor wafer is delivered into a low pressure chemical vapor deposition (LPCVD) tube. Herein, a non-doped or doped amorphous silicon layer is deposited on the surface top of electrodes. A rugged polysilicon capacitance is formed on top of the non-doped or doped amorphous silicon layer by using the methods of rising temperature and decreasing pressure. Then, an ion implantation is applied and follows by a wafer cleaning procedure and an annealing process, wherein those procedures are accomplished after the removal of the wafer from LPCVD tube. During the annealing process, the non-doped or doped amorphous silicon layer is transformed into a polysilicon layer under a temperature roughly about 850.degree.C. In particularly, an in-situ phosphorous doped amorphous silicon can be deposited prior to the formation of non-doped amorphous silicon layer, and won't influence the stages that follow.

Abstract translation: 本发明涉及用于形成用于动态随机存取存储器处理的耐久性多晶硅电容电极的方法。 该方法能够缩短加工时间，提高产量，节省生产成本。 其中，本发明的方法包括：首先，半导体晶片被输送到低压化学气相沉积（LPCVD）管中。 这里，在电极的表面上沉积非掺杂或掺杂的非晶硅层。 通过使用温度升高和压力降低的方法，在非掺杂或掺杂的非晶硅层的顶部形成坚固的多晶硅电容。 然后，通过晶片清洗程序和退火工艺施加离子注入，其中在从LPCVD管去除晶片之后完成这些步骤。 在退火过程中，非掺杂或掺杂的非晶硅层在约850℃的温度下转变成多晶硅层。 特别地，可以在形成非掺杂非晶硅层之前沉积原位磷掺杂的非晶硅，并且不影响随后的阶段。

公开(公告)号：US6066529A

公开(公告)日：2000-05-23

申请号：US198309

申请日：1998-11-23

Applicant: Ping-Wei Lin ,  Jui-Ping Li ,  Ming-Kuan Kao ,  Yi-Fu Chung

Inventor： Ping-Wei Lin ,  Jui-Ping Li ,  Ming-Kuan Kao ,  Yi-Fu Chung

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/8242 ,  H01L21/302 ,  H01L21/28

CPC classification number: H01L28/84 ,  H01L21/32134 ,  H01L27/10852 ,  H01L28/90

Abstract: The present invention provides a method for enlarging the surface area of hemi-spherical grains on the surface of a semiconductor chip. The hemi-spherical grain structure is formed by combining a poly-silicon layer with an underlying amorphous silicon layer. In processing, the two layers are etched with a corrosive solution that etches the amorphous silicon layer at a higher rate than it etches the poly-silicon layer. In this way, a ring-shaped slot forms at the bottom of each hemi-spherical grain thus increasing the total surface area of the hemi-spherical grain structure. Furthermore, surface area of the storage node is increased and the cell capacitor capacitance increases in excess of 15%.

Abstract translation: 本发明提供了一种用于扩大半球芯片表面上的半球形颗粒的表面积的方法。 半球形晶粒结构通过将多晶硅层与下面的非晶硅层组合而形成。 在处理中，用蚀刻非晶硅层的蚀刻溶液蚀刻两层，其腐蚀速度高于蚀刻多晶硅层。 以这种方式，在每个半球形颗粒的底部形成环形槽，从而增加半球形颗粒结构的总表面积。 此外，存储节点的表面积增加，单元电容器电容增加超过15％。

公开(公告)号：US20080124485A1

公开(公告)日：2008-05-29

申请号：US11563568

申请日：2006-11-27

Applicant: CHAO-SHENG CHIANG ,  PING-WEI LIN ,  CHIN-WEI YANG

Inventor： CHAO-SHENG CHIANG ,  PING-WEI LIN ,  CHIN-WEI YANG

IPC: C23C16/513

CPC classification number: C23C16/345 ,  C23C16/401 ,  C23C16/45523

Abstract: Method of successively depositing a multi-film is disclosed. An electric charge removing process is performed after a deposition process of the last film of the multi-film or between the two neighboring film deposition processes. The electric charge removing process includes introducing an inert gas into a reaction chamber of the deposition system and pumping out the inert gas from the reaction chamber.

Abstract translation: 公开了连续沉积多层膜的方法。 在最后的多层膜的沉积处理之后或在两个相邻的膜沉积工艺之间进行电荷去除处理。 电荷去除工艺包括将惰性气体引入沉积系统的反应室并从反应室泵出惰性气体。

公开(公告)号：US20060219924A1

公开(公告)日：2006-10-05

申请号：US11137456

申请日：2005-05-26

Applicant: Tzong-Sheng Lee ,  Ping-Wei Lin ,  Hsiang-Fu Chen ,  Hung-Ti Li ,  Jeng-Long Ou

Inventor： Tzong-Sheng Lee ,  Ping-Wei Lin ,  Hsiang-Fu Chen ,  Hung-Ti Li ,  Jeng-Long Ou

IPC: G01J5/02

CPC classification number: G01J5/04 ,  G01J1/02 ,  G01J1/0252 ,  G01J5/045 ,  G01J5/061 ,  H01L27/14618 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: An infrared imaging sensor and a vacuum packaging method thereof are described. The infrared imaging sensor includes a ceramic base, a metal cap and an infrared filter. The ceramic base has an infrared imaging chip attached thereon and the metal cap includes a getter deposited on an inner surface of the metal cap. The infrared filter seals an opening of the metal cap. The ceramic base, the metal cap and the infrared filter are heated in a vacuum chamber to activate the getter, and to solder the ceramic base, the metal cap and the infrared filter together thereby vacuum packaging the infrared imaging sensor.

Abstract translation: 描述了红外成像传感器及其真空包装方法。 红外成像传感器包括陶瓷基座，金属帽和红外线过滤器。 陶瓷基座上安装有红外成像芯片，金属盖包括沉积在金属盖的内表面上的吸气剂。 红外线过滤器密封金属盖的开口。 陶瓷基座，金属帽和红外线过滤器在真空室中加热以激活吸气剂，并且将陶瓷基底，金属帽和红外线过滤器焊接在一起，从而真空包装红外成像传感器。

公开(公告)号：US06864150B2

公开(公告)日：2005-03-08

申请号：US10384287

申请日：2003-03-06

Applicant: Ping-Wei Lin ,  Gwo-Chyuan Kuoh ,  Chao-Sheng Chiang

Inventor： Ping-Wei Lin ,  Gwo-Chyuan Kuoh ,  Chao-Sheng Chiang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76232

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

Abstract translation: 本发明公开了浅沟槽隔离（STI）的制造方法。 通过利用沉积具有特定厚度和不同消光系数（k）的两层SiON作为ARC，包括：（a）在衬底上沉积衬垫氧化物/氮化硅作为用于蚀刻的硬掩模; （b）在所述氮化硅上沉积一层高消光系数SiON，然后沉积一层低消光系数SiON作为ARC; （c）通过使用STI掩模曝光并显影以形成所述STI的蚀刻掩模; （d）蚀刻所述SiON，氮化硅，衬垫氧化物和所述衬底以形成浅沟槽; （e）在浅沟槽的侧壁和底部生长氧化层，以消除损坏并减少泄漏; （f）在所述浅沟槽和所述氮化硅上沉积氧化物层以填充所述浅沟槽; （g）通过CMP平面化。